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| TDA8295 Digital global standard low IF demodulator for analog TV and FM radio Rev. 01 -- 4 February 2008 Product data sheet 1. General description The TDA8295 is an alignment-free digital multistandard vision and sound low IF signal PLL demodulator for positive and negative video modulation including AM and FM mono sound processing. It can be used in all countries worldwide for M/N, B/G/H, I, D/K, L and L-accent standard. CVBS and SSIF/mono audio is provided via two DACs. FM radio preprocessing is included for simple interfacing with demodulator/stereo decoder backends. The IC is especially suited for the application with the NXP Silicon Tuner TDA8275A or TDA1827x. All the processing is done in the digital domain. The chip has an `easy programming' mode to make the I2C-bus protocol very simple. In principle, only one bit sets the proper standard with recommended content. However, if this is not suitable, free programming is always possible. 2. Features I Digital IF demodulation for all analog TV standards worldwide (M/N, B/G/H, D/K, I, L and L-accent standard) I Multistandard true synchronous demodulation with active carrier regeneration I Alignment-free I 16 MHz typical reference frequency input (from low IF tuner) or operating as crystal oscillator I Internal PLL synthesizer which allows the use of a low-cost crystal (typically 16 MHz) I Especially suited for the NXP Silicon Tuner TDA8275A or TDA1827x I No SAW filter needed I Low application effort and external component count in combination with the TDA8275A or TDA1827x I Pin compatible with predecessor TDA8290 I Simple upgrade of TDA8290 possible I 12-bit IF ADC on chip running with 54 MHz or 27 MHz I Two 10-bit DACs on chip for CVBS and SSIF or audio I Easy programming for I2C-bus I High flexibility due to various I2C-bus programming registers I I2C-bus interface and I2C-bus feed-through for tuner programming I Four I2C-bus addresses selectable via two external pins NXP Semiconductors TDA8295 Digital global standard low IF demodulator for analog TV and FM radio I Gated IF AGC acting on black level by using H/V PLL or peak IF AGC (I2C-bus selectable) I Internal digital logarithmic IF AGC amplifier with up to 48 dB gain and 68 dB control range I Peak search tuner IF AGC for optimal adaptive drive of the IF ADC I Switchable IF PLL and IF AGC loop bandwidths I Precise AFC and lock detector I Accurate group delay equalization for all standards I Very robust IF demodulator coping with adverse field conditions I Wide PLL pull-in range up to 1660 kHz (I2C-bus selectable) I CVBS and SSIF or audio output with simple postfilter (capacitor only) I CVBS gain levelling stage to provide nearly constant signal amplitude during overmodulation I Video equalizer with eight settings I Nyquist filter in video baseband I Excellent video S/N (typically 62 dB weighted) I High selectivity video low-pass filter for all standards I Low video into sound crosstalk I Sound performance comparable to QSS single reference concepts I AM/FM mono sound demodulator I Switchable de-emphasis I Excellent FM sound I Good AM sound I High FM Deviation mode for China I Preprocessing of FM radio (mono and stereo) with highly selective digital band-pass filter I No ceramic filter or external components needed for FM radio I FM radio available in mono I Automatic or forced mute for mono sound I Automatic or forced blank for video I Mostly digital FIR filter implementation (NSC notches and video low-pass filters) I Three GPIO pins I Low total power dissipation (typically 324 mW) I Standby mode (typically 7 mW) I 40-pin HVQFN package I CMOS technology (0.12 m 1.2 V and 3.3 V) 3. Applications I PC TV applications I DVD recorders TDA8295_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 4 February 2008 2 of 77 NXP Semiconductors TDA8295 Digital global standard low IF demodulator for analog TV and FM radio 4. Quick reference data Table 1. Quick reference data Power supplies 3.3 V, 1.2 V; Tamb = 25 C; PC / SC1 for L and M = 10 dB, all others 13 dB; residual picture carrier for L = 3 %, all others 10 %; FM/AM modulation = 54 %, 1 kHz modulation frequency; measured in application PCB (see Figure 12) with 16 MHz crystal frequency, loaded with 75 (CVBS) and 1 k (SSIF/audio). Values are meant for `easy programming' settings (recommended) except internal mono audio and IF demodulation. The low IF spectrum is delivered by a professional downconverter. Symbol VDD(1V2) VDD(3V3) IDD(tot)(1V2) IDD(tot)(3V3) Ptot Parameter supply voltage (1.2 V) supply voltage (3.3 V) total supply current (1.2 V) total supply current (3.3 V) total power dissipation default settings; 75 drive; fs = 54 MHz at ADC; including DAC loads; RRSET = 1 k Power-save mode; fs = 54 MHz at ADC; including DAC loads; RRSET = 2 k; see Section 13.6 Standby mode IF input Vi(p-p) Vi fi peak-to-peak input voltage for full-scale ADC input (0 dBFS) input voltage input frequency operational input related to ADC full scale; all standards; sum of all signals PC / SC1 M/N standard B standard G/H standard I standard DK and L standard L-accent standard FM radio Carrier recovery FPLL B-3dB(cl) fpullin mover(PC) closed-loop -3 dB bandwidth pull-in frequency range picture carrier overmodulation index stop-band suppression group delay equalizer ripple time black for L/L-accent standard; flat field white else video low-pass filter (M/N, B/G/H, I, D/K, L/L-accent standard) peak value for B/G/H half, D/K half, I flat, M (FCC) full, L/L-accent full standard wide [3] [1] [1] Conditions digital and analog digital and analog Min 1.08 2.97 - Typ 1.2 3.3 28 125 434 Max 1.32 3.63 33 136 490 Unit V V mA mA mW Power supply [2] - 324 369 mW 1.8 -3 7 2.0 -3 10 2.2 -3 mW V dBFS 60 830 115 5.75 / 1.25 6.75 / 1.25 7.75 / 2.25 7.75 / 1.75 7.75 / 1.25 1.25 / 7.75 1.25 60 830 117 60 830 - MHz MHz MHz MHz MHz MHz MHz kHz kHz % IF demodulation (video equalizer in Flat mode) sup(stpb) tripple(GDE) -60 20 40 dB ns TDA8295_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 4 February 2008 3 of 77 NXP Semiconductors TDA8295 Digital global standard low IF demodulator for analog TV and FM radio Table 1. Quick reference data ...continued Power supplies 3.3 V, 1.2 V; Tamb = 25 C; PC / SC1 for L and M = 10 dB, all others 13 dB; residual picture carrier for L = 3 %, all others 10 %; FM/AM modulation = 54 %, 1 kHz modulation frequency; measured in application PCB (see Figure 12) with 16 MHz crystal frequency, loaded with 75 (CVBS) and 1 k (SSIF/audio). Values are meant for `easy programming' settings (recommended) except internal mono audio and IF demodulation. The low IF spectrum is delivered by a professional downconverter. Symbol Vo(p-p) Parameter peak-to-peak output voltage Conditions negative PC modulation (all standards except L/L-accent); 75 DC load; sync-white modulation 90 % (nominal) positive PC modulation (L/L-accent standard); 75 DC load; sync-white modulation 97 % (nominal) Bvideo(-3dB) -3 dB video bandwidth overall video response; CVBS equalizer flat all standards except M/N M/N standard resp(f) Gdif dif (S/N)w frequency response differential gain differential phase weighted signal-to-noise ratio video equalizer; 8 equally spaced settings; value at 3.9 MHz 4.8 3.9 -5 58 4.85 4.05 1.5 1.5 62 +4.5 3 3 MHz MHz dB % deg dB 0.8 1.0 1.2 V 0.8 1.0 1.2 V Min Typ Max Unit CVBS output "ITU-T J.63 line 330" "ITU-T J.63 line 330" all standards; unified weighting filter ("ITU-T J.61"); PC at -6 dBFS 1 k DC or AC load; no modulation; PC / SC1 = 13 dB; scaled linearly for all other ratios all standards except B/G/H B/G/H standard FM radio (single carrier) SSIF/mono sound output Vo(SSIF)(RMS) RMS SSIF output voltage 30 27 460 125 35 32 530 143 40 37 610 165 mV mV mV mV Vo(AF)(RMS) RMS AF output voltage 1 k DC or AC load M standard; 54 % modulation degree (13.5 kHz FM deviation before pre-emphasis) B, G/H, I, D, K standard; 54 % modulation degree (27 kHz FM deviation before pre-emphasis) 125 143 165 mV hr(AF) AF headroom before clipping; 1 k DC or AC load M standard; related to 25 kHz peak deviation before pre-emphasis B, G/H, I, D, K standard; related to 50 kHz peak deviation before pre-emphasis 7 7 7 7 7 7 dB dB THD total harmonic distortion FM; for 50 kHz deviation before pre-emphasis (25 kHz for M standard) AM; m = 80 % - 0.1 0.6 0.2 1 % % TDA8295_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 4 February 2008 4 of 77 NXP Semiconductors TDA8295 Digital global standard low IF demodulator for analog TV and FM radio Table 1. Quick reference data ...continued Power supplies 3.3 V, 1.2 V; Tamb = 25 C; PC / SC1 for L and M = 10 dB, all others 13 dB; residual picture carrier for L = 3 %, all others 10 %; FM/AM modulation = 54 %, 1 kHz modulation frequency; measured in application PCB (see Figure 12) with 16 MHz crystal frequency, loaded with 75 (CVBS) and 1 k (SSIF/audio). Values are meant for `easy programming' settings (recommended) except internal mono audio and IF demodulation. The low IF spectrum is delivered by a professional downconverter. Symbol BAF(-3dB) (S/N)w(AF) Parameter -3 dB AF bandwidth AF weighted signal-to-noise ratio Conditions AM FM via internal mono sound demodulator; "ITU-R BS.468-4"; FM mode related to 27 kHz deviation before pre-emphasis; 10 % residual PC; SC1 color bar picture via internal mono sound demodulator; "ITU-R BS.468-4"; AM; m = 54 %; 3 % residual PC; SC1 color bar picture [1] [2] [3] 50 % ADC current; 100 % video DAC current; 50 % sound DAC current. 50 % ADC current; 50 % video DAC current; 25 % sound DAC current. The pull-in range can be doubled to 1660 kHz by I2C-bus register like described in Table 16. Then the AFC read-out has 256 steps. Min 20 40 Typ 27 50 Max - Unit kHz kHz 54 58 - dB 43 46 - dB 5. Ordering information Table 2. Ordering information Package Name TDA8295HN HVQFN40 Description plastic thermal enhanced very thin quad flat package; no leads; 40 terminals; body 6 x 6 x 0.85 mm Version SOT618-1 Type number TDA8295_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 4 February 2008 5 of 77 xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x Product data sheet Rev. 01 -- 4 February 2008 (c) NXP B.V. 2008. All rights reserved. TDA8295_1 6. Functional diagram NXP Semiconductors VIDEO DAC GATED AGC DETECTOR AND INTEGRATOR H/V PLL analog CVBS Digital global standard low IF demodulator for analog TV and FM radio UPSAMPLER low IF signal 2 IF ADC FILTERS AND AGC AMPLIFIER PLL DEMODULATOR NYQUIST SLOPE VIDEO LOW-PASS FILTER VIDEO/ GROUP DELAY EQUALIZER PEAK DETECTOR AND INTEGRATOR SSIF AND FM RADIO BAND-PASS FILTERS SWITCH CORDIC AM/FM SOUND DEMODULATOR UPSAMPLER SOUND DAC analog SSIF or mono sound tuner IF AGC BIT STREAM DAC CLOCK PROCESSOR AND PLL SUPPLY, REFERENCE AND DECOUPLING I2C-BUS crystal or frequency reference I2C-bus 001aah354 TDA8295 6 of 77 Fig 1. Functional diagram of TDA8295 NXP Semiconductors TDA8295 Digital global standard low IF demodulator for analog TV and FM radio 7. Pinning information 7.1 Pinning 39 VDDD(ADC)(3V3) 38 i.c. 33 GPIO0/VSYNC 31 GPIO2/SDA_O 30 TRST_N 29 SDA 28 SCL 27 TCK 26 VSSD2 25 VDDD2(1V2) 24 TMS 23 TDI 22 TDO 21 RST_N RSET 11 VSSA(DAC) 12 V_IOUTN 13 V_IOUTP 14 VDDA(DAC1)(3V3) 15 S_IOUTN 16 S_IOUTP 17 VDDA(DAC2)(3V3) 18 SADDR0 19 SADDR1 20 008aaa095 IF_POS IF_NEG VDDA(ADC)(3V3) VDDD1(1V2) VSSD1 i.c. VDDA(PLL)(1V2) XIN XOUT 1 2 3 4 5 6 7 8 9 TDA8295HN VSSA(PLL) 10 Transparent top view Fig 2. Pin configuration for HVQFN40 Table 3. Pin 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 Pin allocation table Symbol IF_POS VDDA(ADC)(3V3) VSSD1 VDDA(PLL)(1V2) XOUT RSET V_IOUTN VDDA(DAC1)(3V3) S_IOUTP SADDR0 RST_N TDI VDDD2(1V2) TCK SDA Pin 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 Symbol IF_NEG VDDD1(1V2) i.c. XIN VSSA(PLL) VSSA(DAC) V_IOUTP S_IOUTN VDDA(DAC2)(3V3) SADDR1 TDO TMS VSSD2 SCL TRST_N TDA8295_1 36 i.c. terminal 1 index area 32 GPIO1/SCL_O 35 VSSDR 34 VDDDR(3V3) 40 VSSA(ADC) 37 IF_AGC (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 4 February 2008 7 of 77 NXP Semiconductors TDA8295 Digital global standard low IF demodulator for analog TV and FM radio Pin allocation table ...continued Symbol GPIO2/SDA_O GPIO0/VSYNC VSSDR IF_AGC VDDD(ADC)(3V3) Pin 32 34 36 38 40 Symbol GPIO1/SCL_O VDDDR(3V3) i.c. i.c. VSSA(ADC) Table 3. Pin 31 33 35 37 39 7.2 Pin description Table 4. Symbol Reset RST_N 21 I The RST_N input is asynchronous and active LOW, and clears the TDA8295. When RST_N goes LOW, the circuit immediately enters its Reset mode and normal operation will resume four XIN signal falling edges later after RST_N returns HIGH. Internal register contents are all initialized to their default values. The minimum width of RST_N at LOW level is four XIN clock periods. Crystal oscillator input pin. In Slave mode (typically), the XIN input simply receives a 16 MHz clock signal from an external device (typically from the TDA8275A or TDA1827x). In Oscillator mode, a fundamental 16 MHz (typically) crystal is connected between pin XIN and pin XOUT. Crystal oscillator output pin. In Slave mode, the XOUT output is not connected. In Oscillator mode a fundamental 16 MHz (typically) crystal is connected between pin XIN and pin XOUT. I2C-bus bidirectional serial data. SDA is an open-drain output and therefore requires an external pull-up resistor (typically 4.7 k). I2C-bus clock input. SCL is nominally a square wave with a maximum frequency of 400 kHz. It is generated by the system I2C-bus master. These two bits allow to select four possible I2C-bus addresses, and therefore permits to use several TDA8295 in the same application and/or to avoid conflict with other ICs. The complete I2C-bus address is: 1, 0, 0, SADDR1, 0, 1, SADDR0 (see also Section 9.1). SDA_O is equivalent to SDA but can be 3-stated by I2C-bus programming. It is the output of a switch controlled by I2CSW_EN parameter. SDA_O is an open-drain output and therefore requires an external pull-up resistor (see Section 9.3.20). SCL_O is equivalent to SCL input but can be 3-stated by I2C-bus programming. SCL_O is an open-drain output and therefore requires an external pull-up resistor (see Section 9.3.20). For proper functioning of the I2C-bus feed-through, a capacitor C = 33 pF to GND must be added (see Section 13.6). vertical synchronization pulse needed for the NXP Silicon Tuner (see Section 9.3.20) Pin description Pin Type[1][2] Description Reference XIN 8 I XOUT 9 O I2C-bus SDA SCL SADDR0 SADDR1 29 28 19 20 I/O, OD I I I I2C-bus feed-through switch or GPIO GPIO2/SDA_O 31 I/O, OD GPIO1/SCL_O 32 I/O, OD V-sync or GPIO GPIO0/VSYNC Tuner IF AGC IF_AGC TDA8295_1 33 I/O, OD 37 I/O, OD, T tuner IF AGC output (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 4 February 2008 8 of 77 NXP Semiconductors TDA8295 Digital global standard low IF demodulator for analog TV and FM radio Table 4. Symbol Pin description ...continued Pin 24 30 27 23 22 Type[1][2] I I I I O Description Test mode select provides the logic levels needed to change the TAP controller from state to state during the boundary scan test. Test reset is used to reset the TAP controller (active LOW). Grounding is mandatory in Functional mode. Test clock is used to drive the TAP controller. Test data input is the serial data input for the test data instruction. Test data output is the serial test data output pin. The data is provided on the falling edge of TCK. IF positive analog input for internal ADC IF negative analog input for internal ADC positive analog current output of the video output negative analog current output of the video output positive analog current output of the SSIF/mono sound output negative analog current output of the SSIF/mono sound output External bias setting of the DACs. An external resistor (1 k typical) has to be connected between RSET and the analog ground of the board. This resistor generates the current into the DACs and also defines the full scale output current. The total parasitic capacitance seen externally from the RSET pin has to be lower than 20 pF. DAC1 (video DAC) and DAC reference module analog supply voltage (3.3 V typical) DAC2 (sound DAC) analog supply voltage (3.3 V typical) DAC reference module analog ground supply voltage (0 V typical) IF ADC analog supply voltage (3.3 V typical) IF ADC digital supply voltage (3.3 V typical) ADC analog ground supply voltage (0 V typical) ADC, PLL and DACs digital supply voltage (1.2 V typical) ADC, PLL and DACs digital ground supply voltage (0 V typical) crystal oscillator and clock PLL analog supply voltage (1.2 V typical) crystal oscillator and clock PLL analog ground supply voltage (0 V typical) core digital supply voltage (1.2 V typical) core digital ground supply voltage (0 V typical) ring digital supply voltage (3.3 V typical) ring digital ground supply voltage (0 V typical) internally connected; connect to ground internally connected; connect to ground internally connected; connect to ground Boundary scan TMS TRST_N TCK TDI TDO ADC IF_POS IF_NEG DAC V_IOUTP V_IOUTN S_IOUTP S_IOUTN RSET 14 13 17 16 11 AO AO AO AO I 1 2 AI AI Supplies and grounds VDDA(DAC1)(3V3) VDDA(DAC2)(3V3) VSSA(DAC) VDDA(ADC)(3V3) VDDD(ADC)(3V3) VSSA(ADC) VDDD1(1V2) VSSD1 VDDA(PLL)(1V2) VSSA(PLL) VDDD2(1V2) VSSD2 VDDDR(3V3) VSSDR Other pins i.c. i.c. i.c. [1] 15 18 12 3 39 40 4 5 7 10 25 26 34 35 36 38 6 PS PS GND PS PS GND PS GND PS GND PS GND PS GND I I I All digital inputs are 5 V tolerant (except pin XIN). (c) NXP B.V. 2008. All rights reserved. TDA8295_1 Product data sheet Rev. 01 -- 4 February 2008 9 of 77 NXP Semiconductors TDA8295 Digital global standard low IF demodulator for analog TV and FM radio [2] The pin types are defined in Table 5. Table 5. Type AI AO GND I I/O O OD PS T Pin type description Description analog input analog output ground digital input digital input and output digital output open-drain output power supply 3-state 8. Functional description 8.1 IF ADC The low IF spectrum (1 MHz to 10 MHz) from the Silicon Tuner TDA8725A or TDA1827x is fed symmetrically to the 12-bit IF ADC of the TDA8295, where it is sampled with 54 MHz or 27 MHz. All the anti-aliasing filtering is already done in the Silicon Tuner. 8.2 Filters The internal filters permit to reduce the sampling rate to 13.5 MHz, and to form a complex signal to ease the effort of further signal processing. Before this, the DC offset (coming from the ADC) is removed. In addition, standard dependent notch filters for the adjacent sound carriers protect the picture carrier PLL from malfunctioning and avoid disturbances (i.e. moire) becoming visible in the video output. 8.3 PLL demodulator The second-order PLL is the core block of the whole IC. It is very robust against adverse field conditions, like excessive overmodulation, no residual carrier presence or unwanted phase or frequency modulation of the picture carrier. The PLL output is the synchronously demodulated channel. The AFC data is available via the I2C-bus. 8.4 Nyquist filter, video low-pass filter, video and group delay equalizer, video leveling The afore-mentioned down-mixed complex signal at the mixer CORDIC output, already consisting of the demodulated content of the picture carrier together with the sound carriers (the so-called intercarriers), is running through a Nyquist filter to get a flat video response and is made real. Afterwards, a video low-pass filter suppresses the sound carriers and other disturbers. TDA8295_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 4 February 2008 10 of 77 NXP Semiconductors TDA8295 Digital global standard low IF demodulator for analog TV and FM radio Next comes the equalizer circuit to remove the transmitter group delay predistortion. A video leveling stage follows, which brings the output within the SCART specification ( 3dB overall), despite heavy overmodulation. The response time is made very slow. Finally, a video equalizer allows to compensate the perhaps non-flat frequency response from the tuner or to change the overall video response according to customer wish (i.e. peaking or early roll-off). 8.5 Upsampler and video DAC The filtered and compensated CVBS signal is connected to the oversampled 10-bit video DAC (fs = 108 MHz) via an interpolation stage. The strong oversampling replaces a former complicated LCR postfiltering by a simple first-order RC low-pass filter to remove the DAC image frequencies sufficiently. This holds also for the sound DAC, described in Section 8.6. 8.6 SSIF/mono sound processing The complex signal is routed via a band-pass and interpolation filter to the 10-bit sound DAC for the recovery of the second sound carriers (SSIF). A very sharp band-pass filter at 5.5 MHz is added in the FM Radio mode to remove neighbor channels. This also eases the dynamic burden on the following ADC in the demodulator/decoder chip. The afore-mentioned high-selectivity band-pass, which replaces the former ceramic filter, is located behind a frequency shifter. In there, the incoming wanted FM radio channel from the Silicon Tuner is changed from 1.25 MHz to 5.5 MHz. Moreover, the complex signal is demodulated in a linear CORDIC detector and low-pass filtered to attenuate the video spectrum and the second sound carrier, respectively other disturbers above the intercarrier. The output of the linear CORDIC (phase information) is differentiated for getting the demodulated FM audio. The AM demodulation is executed in a synchronous fashion by using a narrow-band PLL demodulator. A de-emphasis filter is implemented for FM standards, before the audio is interpolated to 108 MHz as in the CVBS case. The mono audio is made available in the sound DAC via an I2C-bus controlled selector in case the intercarrier path is not used for driving an external stereo demodulator. However, if the mono audio output has to meet the SCART specification, an external cheap operational amplifier with 12 dB gain becomes necessary, because the low supply voltage for the TDA8295 doesn't allow such high levels like 2 V (RMS) maximum. 8.7 Tuner IF AGC This AGC controls the tuner IF AGC amplifier in the TDA8275A or TDA1827x in such a way, that the IF ADC is always running with a permanent headroom of 3 dB for the sum of all signals present at the ADC input. This ensures an always optimal exploitation of the dynamic range in the IF ADC. The detection is done in peak Search mode during a field period. The attack time is made much faster than the decay time in order to avoid transient clipping effects in the IF ADC. This can happen during channel change or airplane flutter conditions. TDA8295_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 4 February 2008 11 of 77 NXP Semiconductors TDA8295 Digital global standard low IF demodulator for analog TV and FM radio The above wideband, slowly acting AGC loop (uncorrelated) is of first-order integral action. It is closed via the continuous tuner IF AGC amplifier in the Silicon Tuner via a bit stream DAC (PWM signal at 13.5 MHz, 27 MHz or 54 MHz) and an external and uncritical first-order RC low-pass. 8.8 Digital IF AGC Common to both IF AGC concepts is the peak search algorithm as long as the H/V PLL is not locked. This is of advantage for the acquisition by avoiding hang-ups due to excessive overloading, so being able to leave the saturated condition by reducing the gain. Two Detection modes are made available in the IC via I2C-bus. * Black level gated AGC: The first mode uses an IF AGC detector which is gated with a very robust and well-proven H/V sync PLL block on board. Gating occurs on the black level (most of the time on the back porch) of the video signal and the control is delivered after an error integration and exponential weighting to the internal IF AGC amplifier. This IF AGC amplifier, in fact a multiplier, has a control range of -20 dB to +48 dB. * Peak AGC: A fast attack and slow decay action cares for a good and nearly clip-free transient behavior. This proved to be more robust for non-standard signals, like sync clipping along the transmitter/receiver chain. With respect to the IF AGC speed generally, only the gated black level or peak sync IF AGC can be made fast. However the peak search one, used for positive modulation standards (L and L-accent standard), is rather slow because the VITS is present only once in a field. The correlated or narrow-band AGC loop, closed via the continuous IF AGC amplifier in the TDA8295, is of first-order integral action and settles at a constant IF input level with a permanent headroom of 12 dB (picture carrier). This headroom is needed for the own sound carriers and the leaking neighbor (N - 1) spectrum. 8.9 Clock generation Finally, either an external reference frequency (i.e. from the Silicon Tuner) or an own on-chip crystal oscillator in the TDA8295 feeds the internal PLL synthesizer to generate the necessary clock signals. 9. I2C-bus control 9.1 Protocol of the I2C-bus serial interface The TDA8295 internal registers are accessible by means of the I2C-bus serial interface. The SDA bidirectional pin is used as the data input/output pin and SCL as the clock input pin. The highest SCL speed is 400 kHz. TDA8295_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 4 February 2008 12 of 77 NXP Semiconductors TDA8295 Digital global standard low IF demodulator for analog TV and FM radio 9.1.1 Write mode S start BYTE 1 address 0 A ack BYTE 2 start index A ack BYTE 3 data 1 A ack .... BYTE n data n A ack P stop 001aad381 Fig 3. I2C-bus Write mode Table 6. 7 1 Table 7. Field S Byte 1 Address format 6 0 5 0 4 SADDR1 3 0 2 1 1 SADDR0 0 R/W I2C-bus transfer description Bit 7 to 5 4 3 and 2 1 0 Description START condition device address SADDR1 device address SADDR0 R/W = 0 for write action acknowledge start index acknowledge data 1 acknowledge data n acknowledge STOP condition A Byte 2 A Byte 3 A : Byte n A P 7 to 0 7 to 0 7 to 0 - S start BYTE 1 1000 0100 A ack BYTE 2 0000 0001 A ack BYTE 3 0000 0010 A ack P stop 001aah355 a. Address 84h, write 02h in register 01h S start BYTE 1 1000 0100 A ack BYTE 2 0000 0010 A ack BYTE 3 0000 0101 A ack BYTE 4 0000 0100 A ack P stop 001aah356 b. Address 84h, write 05h in register 02h and 04h in register 03h Fig 4. Examples I2C-bus Write mode TDA8295_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 4 February 2008 13 of 77 NXP Semiconductors TDA8295 Digital global standard low IF demodulator for analog TV and FM radio 9.1.2 Read mode S start BYTE 1 address 0 A ack BYTE 2 start index A ack S start BYTE 3 address 1 A ack BYTE 4 value 1 A ack .... BYTE n value n A ack P stop 001aad423 Fig 5. I2C-bus Read mode Table 8. Field S Byte 1 I2C-bus transfer description Bit 7 to 5 4 3 and 2 1 0 A Byte 2 A S Byte 3 7 to 0 7 to 5 4 3 and 2 1 0 A Byte 4 A : Byte n A P 7 to 0 value n acknowledge STOP condition 7 to 0 Description START condition device address SADDR1 device address SADDR0 R/W = 0 for write action acknowledge start index acknowledge START condition (without stop before) device address SADDR1 device address SADDR0 R/W = 1 for read action acknowledge value 1 acknowledge S start BYTE 1 1000 0100 A ack BYTE 2 0000 0010 A ack S start BYTE 3 1000 0101 A ack BYTE 4 0000 0101 A ack BYTE 5 0000 0100 A ack P stop 001aah357 Address 84h, read register 02h with value 05h and read register 03h with value 04h Fig 6. Example I2C-bus Read mode TDA8295_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 4 February 2008 14 of 77 NXP Semiconductors TDA8295 Digital global standard low IF demodulator for analog TV and FM radio 9.2 Register overview The TDA8295 internal registers are accessible by means of the I2C-bus serial interface as described in Section 9.1. In Table 9 and Table 10 an overview of all the registers is given, the register description can be found in Section 9.3. TDA8295_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 4 February 2008 15 of 77 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Product data sheet Rev. 01 -- 4 February 2008 (c) NXP B.V. 2008. All rights reserved. TDA8295_1 NXP Semiconductors Table 9. 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h to 1Bh 1Ch 1Dh I2C-bus registers 7 (MSB) STANDARD[7:0] AGC_SEL PHASE_PER FLL_ON DTO_PC[7:0] DTO_PC[15:8] DTO_PC[23:16] DTO_SC[7:0] DTO_SC[15:8] DTO_SC[23:16] VID_FILT[2:0] D_IF_AGC_ CORR D_IF_AGC_ MODE NOTCH_FILT[4:0] DC_NOTCH GRP_DEL[4:0] RST_INT SBP[3:0] AGC_TRI LIM_ON FLL_LIM[5:0] CAR_DET_LVL[4:0] 0 POL_DET PLL_ON PH_ERR_THRES[3:0] VID_MOD PULL_IN ACTIVE IF_SWAP CAR_DET 6 5 4 3 2 1 0 (LSB) Index Name STANDARD EASY_PROG DIV_FUNC ADC_HEADR PC_PLL_FUNC PC_PLL_THRES PC_PLL_WGT PC_FLL_FUNC CARDET_LEVEL DTO_PC_LOW DTO_PC_MID DTO_PC_HIGH DTO_SC_LOW DTO_SC_MID DTO_SC_HIGH FILTERS_1 FILTERS_2 GRP_DELAY D_IF_AGC_SET_1 D_IF_AGC_SET_2 D_IF_AGC_FORCE T_IF_AGC_SET T_IF_AGC_LIM T_IF_AGC_FORCE T_IF_AGC_FS reserved ADC_HEADR[3:0] PC_PLL_BW[4:0] PHASE_GAIN[6:0] Digital global standard low IF demodulator for analog TV and FM radio D_IF_AGC_AVG[4:0] D_AGC_ERR_ D_IF_AGC_BW[6:0] LIM D_FORCE POL_TIF UP_LIM[3:0] T_FORCE reserved T_FORCE_VAL[6:0] T_IF_AGC_FS[2:0] D_FORCE_VAL[6:0] T_IF_AGC_SPEED[6:0] LOW_LIM[3:0] TDA8295 16 of 77 V_SYNC_DEL CVBS_SET VS_WIDTH[1:0] - VS_POL - VS_DEL[4:0] FOR_BLK AUTO_BLK VID_LVL xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 9. 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh to 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h to 3Bh 3Ch 3Dh 3Eh (c) NXP B.V. 2008. All rights reserved. I2C-bus registers ...continued 7 (MSB) CVBS_LVL[7:0] CVBS_EQ[7:0] ADC_SAT[7:0] AFC[7:0] NOISE_DET MAC_DET FIDT V_LOCK F_H_LOCK N_H_LOCK AM_FM_SND[1:0] DEEMPH[4:0] HD_DK SND_LVL[4:0] SSIF_LVL[4:0] FOR_MUTE AUTO_MUTE SSIF_SND[1:0] 6 5 4 3 2 1 0 (LSB) Product data sheet Rev. 01 -- 4 February 2008 17 of 77 TDA8295_1 NXP Semiconductors Index Name CVBS_LEVEL CVBS_EQ SOUNDSET_1 SOUNDSET_2 SOUND_LEVEL SSIF_LEVEL ADC_SAT AFC HVPLL_STAT D_IF_AGC_STAT T_IF_AGC_STAT reserved ANALOG_DEBUG not used Digital global standard low IF demodulator for analog TV and FM radio D_IF_AGC_STAT[7:0] T_IF_AGC_STAT[7:0] reserved ADC_TEST DAC_TEST - IDENTITY CLB_STDBY reserved ANALOG_STAT ADC_CTL ADC_CTL_2 VIDEODAC_CTL AUDIODAC_CTL PLL_REG00 not used IDENTITY[7:0] GAINSET 0 0 0 LOAD_DACV CS[2:0] B_DA_V[5:0] B_DA_S[5:0] DA_CLK_INV 0 DA_PLL_BYP PLL_AUTO B_REF[3:0] 0 0 0 0 LOAD_DACS PLL_LOCK reserved reserved DCIN TWOS SLEEP PD_ADC PD_DA_V PD_DA_S PD_DA_REF 0 AD_PLL_BYP AD_SR54M STDBY CLB DAC_REF_CLK_CTL - TDA8295 PLL_REG04 not used PLL_REG06 0 CLK_EN BYP_PLL DIRECTO DIRECTI 0 0 0 0 0 PD_PLL xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 9. 3Fh 40h 41h 42h 43h 44h 45h 46h I2C-bus registers ...continued 7 (MSB) MSEL[7:0] NSEL[6:0] 0 GP1_CF[3:0] I2CSW_EN I2CSW_ON CLK_INV_GP2 CLK_INV_GP1 CLK_INV_GP0 0 0 PSEL[4:0] GP0_CF[3:0] GP2_CF[3:0] GP2_VAL GP1_VAL GP0_VAL HF 0 0 0 6 0 5 0 4 0 3 0 2 0 1 0 0 (LSB) 0 Product data sheet Rev. 01 -- 4 February 2008 (c) NXP B.V. 2008. All rights reserved. TDA8295_1 NXP Semiconductors Index Name PLL_REG07 PLL_REG08 PLL_REG09 PLL_REG10 XTALOSC_CTL GPIOREG_0 GPIOREG_1 GPIOREG_2 Digital global standard low IF demodulator for analog TV and FM radio TDA8295 18 of 77 NXP Semiconductors TDA8295 Digital global standard low IF demodulator for analog TV and FM radio I2C-bus register reference Name STANDARD EASY_PROG DIV_FUNC ADC_HEADR PC_PLL_FUNC PC_PLL_THRES PC_PLL_WGT PC_FLL_FUNC CARDET_LEVEL DTO_PC_LOW DTO_PC_MID DTO_PC_HIGH DTO_SC_LOW DTO_SC_MID DTO_SC_HIGH FILTERS_1 FILTERS_2 GRP_DELAY D_IF_AGC_SET_1 D_IF_AGC_SET_2 D_IF_AGC_FORCE T_IF_AGC_SET T_IF_AGC_LIM T_IF_AGC_FORCE T_IF_AGC_FS reserved reserved reserved V_SYNC_DEL CVBS_SET CVBS_LEVEL CVBS_EQ SOUNDSET_1 SOUNDSET_2 SOUND_LEVEL SSIF_LEVEL ADC_SAT AFC HVPLL_STAT D_IF_AGC_STAT T_IF_AGC_STAT I2C-bus access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R R Default value 01h 00h 04h 01h 27h 04h 10h 84h 08h 85h F6h 92h 55h 55h 55h 21h 11h 01h A0h 90h 67h 88h F0h 3Fh 02h 88h 80h 00h 6Fh 01h 73h 08h 21h 02h 08h 04h Reference Table 11 Table 12 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 21 Table 21 Table 22 Table 22 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Table 28 Table 29 Table 30 Table 31 Table 32 Table 33 Table 34 Table 35 Table 36 Table 37 Table 38 Table 39 Table 40 Table 41 Table 42 Table 44 Table 45 Table 46 (c) NXP B.V. 2008. All rights reserved. Table 10. Index 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 27h 28h TDA8295_1 Product data sheet Rev. 01 -- 4 February 2008 19 of 77 NXP Semiconductors TDA8295 Digital global standard low IF demodulator for analog TV and FM radio I2C-bus register reference ...continued Name reserved ANALOG_DEBUG not used IDENTITY CLB_STDBY reserved ANALOG_STAT ADC_CTL ADC_CTL_2 VIDEODAC_CTL AUDIODAC_CTL DAC_REF_CLK_CTL PLL_REG00 not used PLL_REG04 not used PLL_REG06 PLL_REG07 PLL_REG08 PLL_REG09 PLL_REG10 XTALOSC_CTL GPIOREG_0 GPIOREG_1 GPIOREG_2 I2C-bus access R R/W R R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Default value 00h 01h 00h 24h 01h 7Eh 00h 00h 20h 00h 61h 00h 1Ah 02h 01h 00h 11h 01h 07h Reference Table 47 Table 48 Table 49 Table 50 Table 51 Table 52 Table 53 Table 54 Table 55 Table 56 Table 57 Table 58 Table 60 Table 60 Table 60 Table 60 Table 61 Table 62 Table 63 Table 65 Table 10. Index 29h 2Ah 2Bh to 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h to 3Bh 3Ch 3Dh 3Eh 3Fh 40h 41h 42h 43h 44h 45h 46h 9.3 Register description If registers (or bit groups contained in registers) are programmed with invalid values, i.e. values different from those described in the tables below, the default behavior is chosen for the related block. 9.3.1 Standard setting with easy programming With the implemented `easy programming', only one bit sets the TV or FM radio standard with recommended register content. If not suitable however, any of these registers can be written with other settings. With the rising edge of the bit ACTIVE, the registers 02h to 23h are programmed internally with the standard dependent settings according to Table 13. The content of registers with address 24h and higher is untouched. TDA8295_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 4 February 2008 20 of 77 NXP Semiconductors TDA8295 Digital global standard low IF demodulator for analog TV and FM radio Table 11. STANDARD register (address 00h) bit description Legend: * = default value. Bit Symbol Access Value Description TV or FM radio standard selection (easy programming) 0000 0001* 0000 0010 0000 0100 0000 1000 0001 0000 0010 0000 0100 0000 1000 0000 M/N standard B standard G/H standard I standard D/K standard L standard L-accent standard FM radio 7 to 0 STANDARD[7:0] R/W Table 12. EASY_PROG register (address 01h) bit description Legend: * = default value. Bit 0 Symbol ACTIVE Access Value R/W R/W Description not used With the rising edge of this bit, the registers 02h to 23h are programmed with the standard dependent settings (see Table 13). 0* 1 0 to 1 no action no action activate easy programming 7 to 1 - Example: To set the device to B standard e.g., please do the following steps. 1. Write 02h to register STANDARD, address 00h (set B standard) 2. Write 00h to register EASY_PROG, address 01h (make sure that ACTIVE = 0) 3. Write 01h to register EASY_PROG, address 01h (due to 0 to 1 transition of ACTIVE the device is set to B standard, i.e. registers 02h to 23h are programmed automatically according to Table 13) 4. Write 01h to register EASY_PROG, address 01h (reset ACTIVE to logic 0) TDA8295_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 4 February 2008 21 of 77 NXP Semiconductors TDA8295 Digital global standard low IF demodulator for analog TV and FM radio Table 13. Register Easy programming values Standard M/N[1] 04h 01h 27h 04h 10h 84h 08h 85h F6h 92h 55h 55h 55h 21h 11h 01h A0h 90h 88h F0h 02h 88h 80h 00h 6Fh 01h 73h 08h 21h 02h 08h 04h B 04h 01h 27h 04h 10h 84h 08h 00h 00h 80h DAh 4Bh 68h 42h 12h 02h A0h 90h 67h 88h F0h 3Fh 02h 88h 80h 00h 6Fh 01h 73h 08h 22h 02h 04h 04h G/H 04h 01h 27h 04h 10h 84h 08h 7Bh 09h 6Dh DAh 4Bh 68h 44h 12h 02h A0h 90h 67h 88h F0h 3Fh 02h 88h 80h 00h 6Fh 01h 73h 08h 22h 02h 04h 04h I 04h 01h 27h 04h 10h 84h 08h 7Bh 09h 6Dh 1Dh C7h 71h 44h 12h 10h A0h 90h 67h 88h F0h 3Fh 02h 88h 80h 00h 6Fh 01h 73h 08h 22h 02h 04h 04h D/K 04h 01h 27h 04h 10h 84h 08h 7Bh 09h 6Dh 5Fh 42h 7Bh 44h 12h 04h A0h 90h 67h 88h F0h 3Fh 02h 88h 80h 00h 6Fh 01h 73h 08h 22h 02h 04h 04h L 06h 01h 27h 04h 10h 84h 08h 7Bh 09h 6Dh 5Fh 42h 7Bh 44h 12h 08h A0h 90h 67h 88h F0h 3Fh 02h 88h 80h 00h 6Fh 01h 6Ch 08h 44h 02h 04h 04h L-accent 07h 01h 27h 04h 10h 84h 08h 26h B4h 17h 5Fh 42h 7Bh 44h 12h 08h A0h 90h 67h 88h F0h 3Fh 02h 88h 80h 00h 6Fh 01h 6Ch 08h 44h 02h 04h 04h FM radio 00h 01h 22h 04h 10h 04h 08h 00h 00h 80h DAh 4Bh 68h 90h 14h 10h A0h 08h E7h 88h F0h 3Fh 02h 88h 80h 00h 6Fh 04h 73h 10h 22h 02h 02h 04h Index Name 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h [1] DIV_FUNC ADC_HEADR PC_PLL_FUNC PC_PLL_THRES PC_PLL_WGT PC_FLL_FUNC CARDET_LEVEL DTO_PC_LOW DTO_PC_MID DTO_PC_HIGH DTO_SC_LOW DTO_SC_MID DTO_SC_HIGH FILTERS_1 FILTERS_2 GRP_DELAY D_IF_AGC_SET_1 D_IF_AGC_SET_2 T_IF_AGC_SET T_IF_AGC_LIM T_IF_AGC_FS reserved reserved reserved V_SYNC_DEL CVBS_SET CVBS_LEVEL CVBS_EQ SOUNDSET_1 SOUNDSET_2 SOUND_LEVEL SSIF_LEVEL D_IF_AGC_FORCE 67h T_IF_AGC_FORCE 3Fh M/N standard settings are equal to the power-on reset (default) values. TDA8295_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 4 February 2008 22 of 77 NXP Semiconductors TDA8295 Digital global standard low IF demodulator for analog TV and FM radio 9.3.2 Diverse functions (includes tuner IF AGC Pin mode) Table 14. DIV_FUNC register (address 02h) bit description Legend: * = default value. Bit 7 Symbol Access Value Description It determines the tuner IF AGC output Pin mode. The open-drain output can be used in special applications in need of a higher control voltage. 0* 1 6 AGC_TRI R/W Normal mode Open-drain mode When AGC_TRI is set to logic 1 the tuner IF AGC output pin is in 3-state mode. This mode is useful for paralleling a channel decoder for instance. 0* 1 5 and 4 3 2 R/W R/W 0 Normal mode 3-state mode not used reserved, must be set to logic 0 The polarity detector ensures the proper polarity of the video signal. So, the sync impulses of the video output are near ground level. 0 1* 1 VID_MOD R/W 0* 1 0 IF_SWAP R/W polarity detector off polarity detector on Selects video modulation. The only standards with positive video modulation are L and L-accent. negative video modulation positive video modulation When HIGH, the demodulator expects a swapped IF spectrum. This is the case in L-accent standard. This option is also built in for flexibility reasons. 0* 1 normal IF spectrum expected swapped IF spectrum expected AGC_SEL R/W POL_DET R/W 9.3.3 ADC headroom Table 15. ADC_HEADR register (address 03h) bit description Legend: * = default value. Bit Symbol Access Value Description R/W not used ADC_HEADR adjusts the needed headroom for the wanted channel's own sound carriers and the N - 1 adjacent sound carriers (PC in L-accent standard). The ADC headroom is related to the sum of all signals. This function is built in for debugging purposes. 0001* 0010 0100 1000 ADC headroom 3 dB ADC headroom 6 dB ADC headroom 9 dB ADC headroom 12 dB 7 to 4 - 3 to 0 ADC_HEADR[3:0] R/W TDA8295_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 4 February 2008 23 of 77 NXP Semiconductors TDA8295 Digital global standard low IF demodulator for analog TV and FM radio 9.3.4 Picture carrier PLL functions Table 16. PC_PLL_FUNC register (address 04h) bit description Legend: * = default value. Bit Symbol Access Value R/W 0 0001 0 0010 0 0100* 0 1000 1 0000 2 PLL_ON R/W 0 1* 1 PULL_IN R/W 0 1* 0 CAR_DET R/W Description picture carrier PLL loop bandwidth selection loop bandwidth 15 kHz loop bandwidth 30 kHz loop bandwidth 60 kHz loop bandwidth 130 kHz loop bandwidth 280 kHz (for very bad transmitter quality) the picture carrier PLL can be disengaged (e.g. in FM radio standard) PLL off (FM radio) PLL on PULL_IN selects the pull-in range of the picture carrier PLL/FPLL pull-in range 1.66 MHz pull-in range 830 kHz The carrier detector freezes the PLL in case of a picture carrier overmodulation (especially when the picture carrier is very low or disappears). In addition, the picture carrier DTO value is forced to an optimal one to avoid picture carrier phase drift. To adjust the threshold see CAR_DET_LVL. 0* 1 carrier detector off carrier detector on 7 to 3 PC_PLL_BW[4:0] TDA8295_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 4 February 2008 24 of 77 NXP Semiconductors TDA8295 Digital global standard low IF demodulator for analog TV and FM radio Table 17. PC_PLL_THRES register (address 05h) bit description Legend: * = default value. Bit Symbol Access Value Description R/W not used When the settable threshold for the linear phase detector as part of the picture carrier PLL is passed, the phase detector slope is weighted according to the settings in PHASE_GAIN. This feature is of advantage during adverse field conditions. In case multipath happens like ghosts, the PC PLL should not follow the sudden phase jumps. So, the PC PLL is made slow (lower loop bandwidth) with PC_PLL_THRES after surpassing the threshold. This threshold is related to a fraction of FS. There, FS is 90 if PHASE_PER is logic 0 (default) or 180 when logic 1. If the ICPM or ICFM is large because of bad transmitters with oscillator pulling or modulator imbalance, the PC PLL should follow as true as possible. This can be done by increasing the loop bandwidth with overweighting (see PHASE_GAIN, Table 18). 0001 0010 0100* 1000 1 32 1 16 1 8 1 4 7 to 4 - 3 to 0 PH_ERR_THRES[3:0] R/W FS FS FS FS Table 18. PC_PLL_WGT register (address 06h) bit description Legend: * = default value. Bit 7 Symbol PHASE_PER Access Value R/W Description By default, the linear phase detector transfer function is repetitive in . This allows a good picture carrier overmodulation performance, because the PC PLL doesn't need to reacquire the 180 phase modulation, caused by the excessive AM index above m = 100 % (negative residual picture carrier). 0* 1 6 to 0 PHASE_GAIN[6:0] R/W (needed for overmodulation) 2 phase error weighting (adaptive loop speed), see also PH_ERR_THRES in Table 17 for explanation 000 0001 000 0010 000 0100 000 1000 001 0000* 010 0000 100 0000 x 116 x 18 x 14 x 12 flat (no weighting) x2 x4 TDA8295_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 4 February 2008 25 of 77 NXP Semiconductors TDA8295 Digital global standard low IF demodulator for analog TV and FM radio Table 19. PC_FLL_FUNC register (address 07h) bit description Legend: * = default value. Bit 7 Symbol FLL_ON Access Value R/W Description The FLL can be switched off for debugging purposes. In Functional mode, FLL_ON must be logic 1 for all cases. 0 1* 6 LIM_ON R/W FLL off (only for debugging) FLL on The default value is logic 0 to have a normal action FLL. However, some flexibility has been included for field investigations and debugging purposes. 0* 1 5 to 0 FLL_LIM[5:0] R/W limitation off limitation on With these settings, the FLL action can be reduced. For better acquisition behavior, a large value should be chosen. The settings are `don't care' if LIM_ON is logic 0. 00 0001 00 0010 00 0100* 00 1000 01 0000 10 0000 1 4096 1 2048 1 1024 1 512 1 256 1 128 FS FS FS FS FS FS Table 20. CARDET_LEVEL register (address 08h) bit description Legend: * = default value. Bit Symbol Access Value R/W Description not used determines the action threshold of the above carrier detector; if carrier detector is off, CAR_DET_LVL settings are irrelevant 0 0001 0 0010 0 0100 0 1000* 1 0000 X XXXX carrier detector action below 0.5 % residual PC carrier detector action below 1 % residual PC carrier detector action below 2 % residual PC carrier detector action below 4 % residual PC carrier detector action below 8 % residual PC don't care if CAR_DET = 0 7 to 5 - 4 to 0 CAR_DET_LVL[4:0] R/W TDA8295_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 4 February 2008 26 of 77 NXP Semiconductors TDA8295 Digital global standard low IF demodulator for analog TV and FM radio 9.3.5 Picture and sound carrier DTO Table 21. DTO_PC_LOW, DTO_PC_MID and DTO_PC_HIGH register (address 09h to 0Bh) bit description Legend: * = default value. Address Register 09h 0Ah 0Bh DTO_PC_MID Bit Symbol Access Value Description R/W R/W 85h* F6h* 92h* With the digitally tuned picture carrier oscillator (DTO_PC), the IF frequency for the picture carrier demodulation can be set. This function is implemented for general purpose applications which are different from nominal TV standards. It can also be used for debugging purposes. The DTO_PC is part of the picture carrier PLL. To set the DTO_PC value to a certain PC input frequency (fIF), please use the following formula: 13.5 MHz - f IF 24 DTO_PC = ------------------------------------- x 2 . If e.g. the IF 13.5 MHz picture carrier input frequency is 5.75 MHz (M/N standard), one gets 92 F685h as result for DTO_PC. Table 22. DTO_SC_LOW, DTO_SC_MID and DTO_SC_HIGH register (address 0Ch to 0Eh) bit description Legend: * = default value. Address Register 0Ch 0Dh 0Eh DTO_SC_MID Bit Symbol Access Value Description R/W R/W 55h* 55h* 55h* The DTO_SC is part of the FM/AM mono sound demodulator. DTO_SC is calculated in the same way as DTO_PC (described above). In case of M/N standard (sound carrier at 4.5 MHz), one gets 55 5555h for DTO_SC. DTO_SC_LOW 7 to 0 DTO_SC[7:0] 7 to 0 DTO_SC[15:8] DTO_PC_LOW 7 to 0 DTO_PC[7:0] 7 to 0 DTO_PC[15:8] DTO_PC_HIGH 7 to 0 DTO_PC[23:16] R/W DTO_SC_HIGH 7 to 0 DTO_SC[23:16] R/W TDA8295_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 4 February 2008 27 of 77 NXP Semiconductors TDA8295 Digital global standard low IF demodulator for analog TV and FM radio 9.3.6 Filter settings Table 23. FILTERS_1 register (address 0Fh) bit description Legend: * = default value. Bit Symbol Access Value R/W Description video low-pass filter to remove all unwanted frequencies (own sound carriers) above video content (see Figure 7) 001* 010 100 4 to 0 NOTCH_FILT[4:0] R/W video low-pass filter 4 MHz video low-pass filter 5 MHz video low-pass filter off The notch filter attenuates the adjacent sound carrier N - 1, which is located differently dependent on channel spacing 6 MHz, 7 MHz or 8 MHz (see Figure 8). 0 0001* 0 0010 0 0100 1 0000 notch filter for 6 MHz channel spacing (M/N standard) notch filter for 7 MHz channel spacing (B standard) notch filter for 8 MHz channel spacing (G/H, D/K, I, L and L-accent standard) notch/low-pass filter off 7 to 5 VID_FILT[2:0] 10 resp(f) (dB) -10 (1) (2) 001aah358 -30 -50 -70 0 1 2 3 4 5 6 7 f (MHz) (1) M/N standard. (2) All other standards. Fig 7. Video low-pass filters for sound carrier suppression TDA8295_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 4 February 2008 28 of 77 NXP Semiconductors TDA8295 Digital global standard low IF demodulator for analog TV and FM radio 10 resp(f) (dB) 0 -10 -20 -30 -40 -50 -60 0 2 4 6 8 10 (1) (2) (3) 001aah359 12 14 f (MHz) Notch filter for NSC (NPC for L-accent standard) (1) M/N standard. (2) B standard. (3) G/H, D/K, I, L and L-accent standard. Fig 8. Notch filter for adjacent sound carrier suppression Table 24. FILTERS_2 register (address 10h) bit description Legend: * = default value. Bit 4 Symbol Access Value Description R/W 0 1* 3 to 0 SBP[3:0] R/W not used notch filter to remove ADC DC offset off on The SSIF band-pass attenuates unwanted video frequencies, e.g. color carrier. For FM radio standard it provides almost channel selectivity (see Figure 9). 0001* 0010 0100 1000 SSIF band-pass 4.5 MHz (M/N standard) SSIF band-pass 6.2 MHz (all other TV standards) SSIF band-pass 5.5 MHz high selectivity (FM radio) SSIF band-pass off 7 to 5 - DC_NOTCH R/W TDA8295_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 4 February 2008 29 of 77 NXP Semiconductors TDA8295 Digital global standard low IF demodulator for analog TV and FM radio 10 resp(f) (dB) -10 (1) (2) (3) 001aah360 -30 -50 -70 0 2 4 6 8 10 12 14 f (MHz) (1) M/N standard. (2) All other standards. (3) FM radio. Fig 9. SSIF and FM radio band-pass filters 9.3.7 Group delay equalization Table 25. GRP_DELAY register (address 11h) bit description Legend: * = default value. Bit Symbol Access Value R/W R/W 0 0001* 0 0010 0 0100 0 1000 1 0000 Description not used group delay equalization to correct the transmitter predistortion group delay M/N standard group delay B/G/H standard group delay D/K standard group delay L/L-accent standard group delay I (flat) standard 7 to 5 4 to 0 GRP_DEL[4:0] TDA8295_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 4 February 2008 30 of 77 NXP Semiconductors TDA8295 Digital global standard low IF demodulator for analog TV and FM radio 9.3.8 Digital IF AGC functions Table 26. D_IF_AGC_SET_1 register (address 12h) bit description Legend: * = default value. Bit 7 Symbol D_IF_AGC_CORR Access Value R/W Description This determines the condition under which the digital IF AGC switches to Correlated mode. If D_IF_AGC_CORR is HIGH, the digital IF AGC works in a Correlated mode only if N_H_LOCK, F_H_LOCK and V_LOCK are active (see H/V PLL read-out in Table 44). If LOW, the Correlated mode is activated when N_H_LOCK and V_LOCK are active. 0 1* 6 D_IF_AGC_MODE R/W H-lock + V-lock H-lock + fast H-lock + V-lock If HIGH, the digital IF AGC detection and gating is done during the back porch of the video signal. This Detection mode can be used for all standards (also L/L-accent standard) without impact on the IF AGC loop speed. 0* 1 5 to 1 D_IF_AGC_AVG[4:0] R/W peak sync AGC (slow peak white L/L-accent standard) black level AGC detection With D_IF_AGC_AVG the number of lines for averaging during the digital IF AGC gating window is set. This is only valid if the AGC mode is correlated (H/V PLL locked). With the averaging, the line noise at low RF levels is reduced. 0 0001 0 0010 0 0100 0 1000 1 0000* 0 RST_INT R/W 2 samples 4 samples 8 samples 16 samples 32 samples The digital IF AGC integrator can be set to zero (i.e. lowest digital IF AGC gain). This option can be used for debugging purposes. 0* 1 normal operation reset IF AGC integrator TDA8295_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 4 February 2008 31 of 77 NXP Semiconductors TDA8295 Digital global standard low IF demodulator for analog TV and FM radio Table 27. D_IF_AGC_SET_2 register (address 13h) bit description Legend: * = default value. Bit 7 Symbol D_AGC_ERR_LIM Access Value R/W Description With D_AGC_ERR_LIM the digital IF AGC error slope is limited. This can improve performance under the presence of e.g. impulsive noise that can confuse the AGC detector. 0 1* 6 to 0 D_IF_AGC_BW[6:0] R/W 000 0001 000 0010 000 0100 000 1000 001 0000* 010 0000 100 0000 limitation off limitation on digital IF AGC 3 dB-loop bandwidth setting 25 Hz 50 Hz 100 Hz 200 Hz 400 Hz 800 Hz 1.6 kHz Table 28. D_IF_AGC_FORCE register (address 14h) bit description Legend: * = default value. Bit 7 Symbol D_FORCE Access Value Description R/W 0* 1 6 to 0 D_FORCE_VAL[6:0] R/W the IF AGC output voltage can be forced externally to a fixed voltage, determined by IF_AGC_EXT IF AGC normal operation IF AGC output voltage determined by D_FORCE_VAL This determines the digital IF AGC forced value and is a `don't care' if D_FORCE is LOW. The format is twos complement. The default is 67h, which equals 0 dB internal gain. In the following some possible settings for 6 dB gain steps are shown. 51h 5Ch 67h* 72h 7Dh 08h 13h 1Eh 29h 34h 3Fh XXh -12 dB -6 dB 0 dB +6 dB +12 dB +18 dB +24 dB +30 dB +36 dB +42 dB +48 dB don't care if D_FORCE = 0 TDA8295_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 4 February 2008 32 of 77 NXP Semiconductors TDA8295 Digital global standard low IF demodulator for analog TV and FM radio 9.3.9 Tuner IF AGC functions Table 29. T_IF_AGC_SET register (address 15h) bit description Legend: * = default value. Bit 7 Symbol POL_TIF Access Value R/W 0 1* Description tuner IF AGC polarity inverted tuner IF AGC polarity normal tuner IF AGC polarity: the higher the necessary gain, the higher the IF AGC voltage T_IF_AGC_SPEED determines the tuner IF AGC loop speed 000 0001 000 0010 000 0100 000 1000* 001 0000 010 0000 100 0000 -18 dB nominal -12 dB nominal -6 dB nominal nominal speed (determined by the tuner IF control slope) +6 dB nominal +12 dB nominal +18 dB nominal 6 to 0 T_IF_AGC_SPEED[6:0] R/W Table 30. T_IF_AGC_LIM register (address 16h) bit description Legend: * = default value. Bit Symbol Access Value R/W Description The tuner IF AGC output voltage can be limited to interface with concepts having power supply < 3.3 V. UP_LIM determines the upper limit from 12 FS (= 0h) to FS (= Fh). The format is straight binary. 1111* 3 to 0 LOW_LIM[3:0] R/W set upper limit to maximum LOW_LIM determines the lower tuner IF AGC output limit from 0 (= 0h) to 12 FS (= Fh). The format is straight binary. 0000* set lower limit to minimum 7 to 4 UP_LIM[3:0] Table 31. T_IF_AGC_FORCE register (address 17h) bit description Legend: * = default value. Bit 7 Symbol T_FORCE Access Value R/W Description the tuner IF AGC output voltage can be forced externally to a fixed voltage, determined by T_FORCE_VAL 0* 1 6 to 0 T_FORCE_VAL[6:0] R/W tuner IF AGC normal operation tuner IF AGC output voltage determined by T_FORCE_VAL T_FORCE_VAL determines the tuner IF AGC forced value. So the tuner IF AGC can be fixed to a certain value for debugging purposes. Format is straight binary. 3Fh* XXh TDA8295_1 0.5 x VDD(3V3), i.e. 1.65 V nominally don't care if T_FORCE = 0 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 4 February 2008 33 of 77 NXP Semiconductors TDA8295 Digital global standard low IF demodulator for analog TV and FM radio Table 32. T_IF_AGC_FS register (address 18h) bit description Legend: * = default value. Bit Symbol Access Value R/W R/W Description not used by increasing the IF AGC noise shaper sampling rate (fs), the noise shaper in-band disturbance (line clamping noise) can be heavily reduced 000 010* 100 fs = 13.5 MHz fs = 27 MHz fs = 54 MHz 7 to 3 2 to 0 T_IF_AGC_FS[2:0] 9.3.10 V-sync adjustment Table 33. V_SYNC_DEL register (address 1Ch) bit description Legend: * = default value. Bit Symbol Access Value Description VS_WIDTH determines the width (in horizontal lines) of the V-sync gating pulse (needed for gating of tuner RF AGC2) 00 01* 10 11 5 VS_POL R/W width 1 line (64 s) width 2 lines width 4 lines width 16 lines VS_POL determines the polarity of the V-sync pulse: if VS_POL = 1, the first edge of the pulse is positive, else negative. 0 1* 4 to 0 VS_DEL[4:0] R/W first edge negative first edge positive VS_DEL determines the first edge position of the output V-sync pulse compared to the beginning of the vertical blanking interval: pulse_position = ( VS_DEL - 12 ) lines 0Fh* first edge 3 lines after beginning of vertical interval 7 and 6 VS_WIDTH[1:0] R/W TDA8295_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 4 February 2008 34 of 77 NXP Semiconductors TDA8295 Digital global standard low IF demodulator for analog TV and FM radio 9.3.11 CVBS settings Table 34. CVBS_SET register (address 1Dh) bit description Legend: * = default value. Bit 2 Symbol FOR_BLK Access Value Description R/W R/W 0* 1 1 AUTO_BLK R/W 0* 1 0 VID_LVL R/W not used when active, the video output is always blanked, e.g. for channel change (forced blank) no action video blanked when active, the video output is blanked if the horizontal line lock flag (N_H_LOCK, see Table 44) is not present auto-blanking off auto-blanking on the video levelling stage ensures a constant and clipping free video output level (important for excessive picture carrier overmodulation) 0 1* video levelling stage off video levelling stage on 7 to 3 - Table 35. CVBS_LEVEL register (address 1Eh) bit description Legend: * = default value. Bit Symbol Access Value Description With this byte, the nominal video output level is freely programmable. The format is unsigned integer (offset binary). Settings below 40h and above C0h, which correspond to -5 dB (40h) and +4.5 dB (C0h) related to the default value, are forbidden. In the following some possible settings in 1 dB steps are shown. 51h 5Bh 66h 73h* 81h 91h A2h -3 dB nominal -2 dB nominal -1 dB nominal nominal: 1 V (p-p) video output level (sync-peak) +1 dB nominal +2 dB nominal +3 dB nominal 7 to 0 CVBS_LVL[7:0] R/W TDA8295_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 4 February 2008 35 of 77 NXP Semiconductors TDA8295 Digital global standard low IF demodulator for analog TV and FM radio Table 36. CVBS_EQ register (address 1Fh) bit description Legend: * = default value. Bit Symbol Access Value Description The video equalizer can be used for the compensation of a principal tuner tilt or to change the video frequency according to customer taste. The figures given are at 5 MHz CVBS with respect to low frequencies (see Figure 10). 0000 0001 0000 0010 0000 0100 0000 1000* 0001 0000 0010 0000 0100 0000 1000 0000 The video frequency response is -8 dB for 5 MHz. The video frequency response is -6 dB for 5 MHz. The video frequency response is -4 dB for 5 MHz. The video frequency response is -2 dB for 5 MHz. The video frequency response is made flat in this mode. The video frequency response is +2 dB (peaking) for 5 MHz. The video frequency response is +4 dB (peaking) for 5 MHz. The video frequency response is +6 dB (peaking) for 5 MHz. 7 to 0 CVBS_EQ[7:0] R/W 10 resp(f) (dB) 6 001aah361 2 -2 -6 -10 0 1 2 3 4 5 6 7 f (MHz) Fig 10. Video equalizer curves TDA8295_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 4 February 2008 36 of 77 NXP Semiconductors TDA8295 Digital global standard low IF demodulator for analog TV and FM radio 9.3.12 SSIF and mono sound settings Table 37. SOUNDSET_1 register (address 20h) bit description Legend: * = default value. Bit 7 Symbol Access Value R/W R/W 01* 10 XX 4 to 0 DEEMPH[4:0] R/W Description not used Output mode for inbuilt FM/AM mono sound demodulator FM sound AM sound (only L/L-accent standard) don't care if SSIF output is chosen (SSIF_SND[1:0] = 10) mono sound de-emphasis adjustment to compensate transmitter pre-emphasis; or low-pass filter to remove out of audio band interferers 0 0001* de-emphasis of 75 s for M/N standard or non-European FM radio to compensate the transmitter pre-emphasis de-emphasis of 50 s for B/G/H, D/K and I standard or European FM radio to compensate the transmitter pre-emphasis low-pass filter with 30 kHz -3 dB cut-off frequency to remove out of audio band interferers low-pass filter with 140 kHz -3 dB cut-off frequency to drive an external BTSC stereo decoder The de-emphasis filter is bypassed. This can be used for debugging or other purposes. 6 and 5 AM_FM_SND[1:0] 0 0010 0 0100 0 1000 1 0000 Table 38. SOUNDSET_2 register (address 21h) bit description Legend: * = default value. Bit 7 to 5 4 Symbol HD_DK Access Value R/W R/W Description not used When active, the internal FM mono sound demodulator can handle excessive FM deviations up to 400 kHz. This might happen in D/K standard China. To activate this mode, it is mandatory to set D/K standard first. The sound output level has to be adapted accordingly by the microprocessor to avoid sound DAC clipping. E.g. for 400 kHz FM deviation, the -12 dB setting of the sound level register (see Table 39) is recommended. 0* 1 X high Deviation mode off high Deviation mode on don't care if SSIF output is chosen (SSIF_SND[1:0] = 10) TDA8295_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 4 February 2008 37 of 77 NXP Semiconductors TDA8295 Digital global standard low IF demodulator for analog TV and FM radio Table 38. SOUNDSET_2 register (address 21h) bit description ...continued Legend: * = default value. Bit 3 Symbol FOR_MUTE Access Value R/W Description When active, the mono sound signal is always muted. This setting only makes sense in case the sound DAC output is also set to mono sound (SSIF_SND[1:0] = 01). FOR_MUTE has no function if SSIF_SND[1:0] = 10. 0* 1 X 2 AUTO_MUTE R/W off on don't care if SSIF output is chosen (SSIF_SND[1:0] = 10) When active, the mono sound signal is muted if the horizontal lock flag (N_H_LOCK) disappears. This setting only makes sense in case the sound DAC output is also set to mono sound (SSIF_SND[1:0] = 01). FOR_MUTE has no function if SSIF_SND[1:0] =10. 0* 1 X 1 and 0 SSIF_SND[1:0] R/W 01 10* off on don't care if SSIF output is chosen (SSIF_SND[1:0] = 10) either mono sound or SSIF can be chosen for the sound DAC output mono sound SSIF Table 39. SOUND_LEVEL register (address 22h) bit description Legend: * = default value. Bit Symbol Access Value R/W 0 0001 Description not used mono sound output level -12 dB nominal; implemented for flexibility reasons. With this setting, the adaptation to different standard requirements can be done. -6 dB nominal; implemented for flexibility reasons. With this setting, the adaptation to different standard requirements can be done. It is chosen for FM radio because of the large FM deviation involved. Nominal setting; FM deviations up to 100 kHz can be processed without sound DAC clipping. The clipping level is 535 mV (RMS) typically. +6 dB nominal; chosen for M/N standard due to less nominal frequency deviation +12 dB nominal; implemented for flexibility reasons. With this setting, the adaptation to different standard requirements can be done. don't care if SSIF output is chosen (SSIF_SND[1:0] = 10) 7 to 5 - 4 to 0 SND_LVL[4:0] R/W 0 0010 0 0100 0 1000* 1 0000 X XXXX TDA8295_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 4 February 2008 38 of 77 NXP Semiconductors TDA8295 Digital global standard low IF demodulator for analog TV and FM radio Table 40. SSIF_LEVEL register (address 23h) bit description Legend: * = default value. Bit Symbol Access Value R/W 0 0001 Description not used SSIF output level -12 dB nominal; implemented for flexibility reasons. With this setting, the adaptation to different standard requirements can be done. -6 dB nominal; implemented for flexibility reasons. With this setting, the adaptation to different standard requirements can be done. Nominal setting; typical output level is 55 mV (RMS) for PC / SC ratio of 13 dB (see Section 12). +6 dB nominal; implemented for flexibility reasons. With this setting, the adaptation to different standard requirements can be done. +12 dB nominal; implemented for flexibility reasons. With this setting, the adaptation to different standard requirements can be done. don't care if mono sound output is chosen (SSIF_SND[1:0] = 01) 7 to 5 - 4 to 0 SSIF_LVL[4:0] R/W 0 0010 0 0100* 0 1000 1 0000 X XXXX 9.3.13 Status registers: ADC saturation, AFC, H/V PLL and AGC Table 41. Bit ADC_SAT register (address 24h) bit description Access Value Description With ADC_SAT, the ADC saturation percentage in a period of 40 ms can be calculated by the following ADC_SAT formula: saturation = ------------------------ (%) . 256 Table 42. Bit AFC register (address 25h) bit description Access Value R Description This is the readout for AFC. AFC contains the frequency deviation from nominal IF picture carrier. The format is twos complement, 13.2 kHz steps are done per LSB. See Table 43 for details. The frequency deviation could also be given by the following formula: - AFC x 6 750 f IF - f nom = --------------------------------- (kHz) . For a frequency 256 deviation from the nominal IF picture carrier greater than the FPLL pull-in capability (-830.6 kHz to +843.8 kHz or -1674.3 kHz to +1687.5 kHz), the output reading is undefined. The AFC lock indication can be taken from the N_H_LOCK information from the H-sync PLL. The lock occurs inside a frequency window, which is determined by the pull-in capability of the FPLL. Symbol 7 to 0 ADC_SAT[7:0] R Symbol 7 to 0 AFC[7:0] TDA8295_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 4 February 2008 39 of 77 NXP Semiconductors TDA8295 Digital global standard low IF demodulator for analog TV and FM radio Calculation of frequency deviation from AFC value Table 43. Deviation from nominal AFC[7] AFC[6] AFC[5] AFC[4] AFC[3] AFC[2] AFC[1] AFC[0] IF frequency[1] fIF = fnom - 1674.3 kHz fIF = fnom - 1661.1 kHz : fIF = fnom - 830.6 kHz fIF = fnom - 817.4 kHz : fIF = fnom - 13.2 kHz fIF = fnom fIF = fnom + 13.2 kHz : fIF = fnom + 830.6 kHz fIF = fnom + 843.8 kHz : fIF = fnom + 1674.3 kHz fIF = fnom + 1687.5 kHz [1] 0 0 : 0 0 : 0 0 1 : 1 1 : 1 1 1 1 : 0 0 : 0 0 1 : 1 1 : 0 0 1 1 : 1 1 : 0 0 1 : 0 0 : 0 0 1 1 : 1 1 : 0 0 1 : 0 0 : 0 0 1 1 : 1 1 : 0 0 1 : 0 0 : 0 0 1 1 : 1 1 : 0 0 1 : 0 0 : 0 0 1 1 : 1 1 : 0 0 1 : 0 0 : 0 0 1 0 : 1 0 : 1 0 1 : 1 0 : 1 0 See Section 12 for nominal IF frequencies. Table 44. Bit 5 7 and 6 - HVPLL_STAT register (address 26h) bit description Symbol Access Value R Description not used This flag gets HIGH in case the video S/N (weighted) drops below 30 dB. For proper and noise free video signals it stays LOW. It can be used for debugging and other purposes. This flag indicates the presence of copy-guarded video content from STBs or VCRs. It can be used for debugging and other purposes. This flag indicates the frame rate (50 Hz or 60 Hz). When active, 60 Hz is detected. It can be used for debugging and other purposes. This flag is active, if a proper frame (50 Hz or 60 Hz) is detected. It can be used for debugging and other purposes. This flag is active, if a proper H-sync (15.625 kHz or 15.734 kHz) is detected (Fast mode). It can be used for debugging and other purposes. This flag is active, if a proper H-sync (15.625 kHz or 15.734 kHz) is detected (Normal mode). It can be used for debugging and other purposes. NOISE_DET R 4 MAC_DET R - 3 FIDT R - 2 V_LOCK R - 1 F_H_LOCK R - 0 N_H_LOCK R - TDA8295_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 4 February 2008 40 of 77 NXP Semiconductors TDA8295 Digital global standard low IF demodulator for analog TV and FM radio D_IF_AGC_STAT register (address 27h) bit description Access Value Description D_IF_AGC_STAT is the digital IF AGC status readout byte. Contains the digital IF AGC loop DC information. The format is twos complement. To get the internal gain in dB, the following formula can be used: D_IF_AGC_STAT + 50 gain = ------------------------------------------------------- (dB) . 3.675 Table 45. Bit Symbol 7 to 0 D_IF_AGC_STAT[7:0] R Table 46. Bit T_IF_AGC_STAT register (address 28h) bit description Access Value R Description T_IF_AGC_STAT is the IF AGC status readout byte. Contains the tuner IF AGC loop DC information. The format is offset binary. Symbol 7 to 0 T_IF_AGC_STAT[7:0] 9.3.14 Debug register for ADC and DAC test Table 47. ANALOG_DEBUG register (address 2Ah) bit description Legend: * = default value. Bit 1 Symbol Access Value R/W Description not used If ADC_TEST is HIGH, the ADC input signal is interpolated to 108 MHz and fed to video and sound DAC output; the main circuitry is bypassed. This feature is intended mainly for debugging purposes and performance judgment. 0* 1 0 DAC_TEST R/W Normal mode ADC Test mode DAC Test mode; in this test mode an internally generated sine wave is given out to video and sound DAC. The amplitude at DAC output is -1.7 dBFS. The frequency can be set by DTO_PC. Please use the following formula: DTO_PC f = --------------------- x 13.5 MHz . Due to the sampling theorem 24 2 only frequencies up to 6.75 MHz can be generated. This feature is intended mainly for debugging purposes and performance judgment. 0* 1 X Normal mode DAC Test mode don't care if ADC_TEST = 1 7 to 2 - ADC_TEST R/W 9.3.15 Chip identification and Standby mode Table 48. Bit IDENTITY register (address 2Fh) bit description Access Value Description 1000 1010 chip identification, value corresponds to TDA8295 Symbol 7 to 0 IDENTITY[7:0] R TDA8295_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 4 February 2008 41 of 77 NXP Semiconductors TDA8295 Digital global standard low IF demodulator for analog TV and FM radio Table 49. CLB_STDBY register (address 30h) bit description Legend: * = default value. Bit 1 Symbol Access Value R/W STDBY R/W Description not used When STDBY is set to logic 1, the chip enters in Standby mode, and its power consumption is reduced. The IF AGC pin is set to high-ohmic. The default value is logic 0, which means that the chip is active. 0* 1 0 CLB R/W Normal mode Standby mode This signal clears the TDA8295 through the I2C-bus interface (software reset). To activate the reset, just write CLB = 0. This software reset will not affect the content of the registers. 0 1* activate soft reset normal operation 7 to 2 - 9.3.16 Status of clock PLL and video/sound DAC load Table 50. Bit 7 6 ANALOG_STAT register (address 32h) bit description Access Value R 0 1 5 LOAD_DACS R 0 1 4 PLL_LOCK R 0 1 3 to 0 R Description not used output load identification video DAC Normal mode If active, the video DAC output voltage is above reference voltage. output load identification sound DAC Normal mode If active, the sound DAC output voltage is above reference voltage. clock PLL lock indicator clock PLL unlocked indicates that the clock PLL is locked reserved Symbol LOAD_DACV R TDA8295_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 4 February 2008 42 of 77 NXP Semiconductors TDA8295 Digital global standard low IF demodulator for analog TV and FM radio 9.3.17 ADC control In the TDA8295 a 12-bit ADC is implemented sampling with a 54 MHz clock (27 MHz optional). Table 51. ADC_CTL register (address 33h) bit description Legend: * = default value. Bit 7 Symbol Access Value Description The track and hold circuit in the converter has a programmable gain setting, which is controlled by the GAINSET parameter. In case the gain of the track and hold is increased, the input range of the ADC is decreased accordingly. 0* 1 6 to 4 CS[2:0] R/W 2.0 V (p-p) 1.0 V (p-p) (6 dB gain) The current consumption of the ADC can be programmed with these two bits. It is possible to increase or decrease the current by the following ratio: 000 001 010* 011 100 101 110 111 3 DCIN R/W not allowed not allowed 0.50 (recommended for 54 MHz sampling) 0.75 1.00 1.25 1.50 not allowed The input signal of the ADC can be either AC coupled by means of two capacitors or connected directly to the inputs (DC coupled). 0* 1 2 TWOS R/W 0 1* 1 SLEEP R/W AC coupling DC coupling This parameter controls the output format of the ADC. offset binary format twos complement format When HIGH, SLEEP sets the ADC into its Sleep mode. Both bias current and clock are switched off. In this mode, the current consumption is reduced by a factor of 6. The reference circuit will remain active in order to guarantee a fast recovery from Sleep mode. 0* 1 0 PD_ADC R/W Normal mode ADC Sleep mode When HIGH, PD_ADC sets the ADC into its Power-down mode. All internal currents are switched off. In this mode, the current consumption is near zero (leakage current only). 0* 1 Normal mode ADC Power-down mode GAINSET R/W TDA8295_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 4 February 2008 43 of 77 NXP Semiconductors TDA8295 Digital global standard low IF demodulator for analog TV and FM radio Table 52. ADC_CTL_2 register (address 34h) bit description Legend: * = default value. Bit 1 Symbol Access Value R/W Description not used The clock PLL can be bypassed for the ADC sampling clock. Then the crystal output is directly taken for ADC sampling. 0* 1 0 AD_SR54M R/W 0 1* Normal mode Bypass mode AD_SR54M sets the ADC sampling rate ADC sampling rate 27 MHz; first decimation filter is bypassed ADC sampling rate 54 MHz 7 to 2 - AD_PLL_BYP R/W 9.3.18 Video and sound DAC control The TDA8295 implements two 10-bit DAC modules (CVBS and sound outputs) which are sampled by a 108 MHz clock. A reference module derives biasing currents for the two DACs. Table 53. VIDEODAC_CTL register (address 35h) bit description Legend: * = default value. Bit 7 Symbol Access Value R/W 0 Description reserved, must be set to logic 0 B_DA_V is the coarse output level adjustment parameters of the video DAC. See Section 13.3. 00 0000 11 1111* 0 PD_DA_V R/W 0* 1 minimum current setting maximum current setting When HIGH, PD_DA_V sets the video DAC into its Power-down mode. Normal mode video DAC Power-down mode 6 to 1 B_DA_V[5:0] R/W Table 54. AUDIODAC_CTL register (address 36h) bit description Legend: * = default value. Bit 7 Symbol Access Value R/W 0 Description reserved, must be set to logic 0 B_DA_S is the coarse output level adjustment parameters of the sound DAC. See Section 13.3. 00 0000* 11 1111 0 PD_DA_S R/W 0* 1 minimum current setting maximum current setting When HIGH, PD_DA_S sets the sound DAC into its Power-down mode. Normal mode sound DAC Power-down mode 6 to 1 B_DA_S[5:0] R/W TDA8295_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 4 February 2008 44 of 77 NXP Semiconductors TDA8295 Digital global standard low IF demodulator for analog TV and FM radio Table 55. DAC_REF_CLK_CTL register (address 37h) bit description Legend: * = default value. Bit 7 6 Symbol Access Value R/W Description not used For debugging purposes, the DAC clock polarity can be inverted. 0 1* 5 DA_PLL_BYP R/W inverted polarity normal polarity If active, the clock PLL for DAC sampling can be bypassed. Then, the crystal output is directly taken for DAC sampling. 0* 1 4 to 1 B_REF[3:0] R/W Normal mode Bypass mode For accuracy, one external resistor connected to pin RSET and board ground controls the bias current. Moreover, B_REF permits to adjust this bias current from -7 % to +7 % (see Section 13.3). Format is signed binary. 1111 0000* 0111 0 PD_DA_REF R/W 0* 1 minimum fine current nominal fine current maximum fine current When HIGH, PD_DA_REF sets the reference module into its Power-down mode. Normal mode Power-down mode DA_CLK_INV R/W TDA8295_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 4 February 2008 45 of 77 NXP Semiconductors TDA8295 Digital global standard low IF demodulator for analog TV and FM radio 9.3.19 Clock generation (PLL and crystal oscillator) The TDA8295 implements a crystal oscillator which can be used either in Slave mode or in Oscillator mode (see Section 13.7), and a multipurpose PLL which receives XIN as input clock, and delivers the system clock of the IC (108 MHz). Table 56. PLL_REG00 register (address 38h) bit description Legend: * = default value. Bit 5 Symbol PLL_AUTO Access Value R/W R/W 0 00 Description reserved, must be set to logic 00 clock PLL mode control The sequencing of the programming and monitoring of the PLL can be made `manually' through CLK_EN, BYP_PLL, PD_PLL and LOCK, according to the following set of instructions: After a hardware reset: 7 and 6 - * * Set PLL_AUTO to logic 0 By default, CLK_EN = BYP_PLL = PD_PLL = 1, LOCK = 0, the PLL is in Power-down mode, is not locked, and the output clock is the clock of the quartz oscillator used to resynchronize reset signals in the TDA8295 Set BYP_PLL and CLK_EN to logic 0 Set MSEL, NSEL and PSEL that are corresponding to the frequency required value Set PD_PLL to logic 0, in order that the PLL takes those parameters into account and starts up Then, wait for a minimum time of 500 s (which is the maximum time the PLL should take to lock). This time could be used to make the programming of the other I2C-bus registers. Set CLK_EN to logic 1 to enable the sampling frequency to the rest of the chip Optionally, verify that LOCK = 1 Then: * * * * * * 1* The sequencing of the programming and monitoring of the PLL is handled automatically by the TDA8295 at initialization and each time one of the M, N, P parameters is changed. Thus, the user has only to program M, N, P and then once the PLL is locked, its output clock becomes enabled automatically. reserved, must be set to logic 0 0000 4 to 0 Table 57. Bit 7 to 3 2 to 0 - R/W 0 0000 PLL_REG04 register (address 3Ch) bit description Symbol Access Value R/W R/W 000 Description not used reserved, must be set to logic 000 TDA8295_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 4 February 2008 46 of 77 NXP Semiconductors TDA8295 Digital global standard low IF demodulator for analog TV and FM radio Table 58. PLL_REG06 register (address 3Eh) bit description Legend: * = default value. Bit 7 6 Symbol CLK_EN Access Value R/W R/W 0 1* X 5 BYP_PLL R/W 0 Description reserved, must be set to logic 0 CLK_EN controls the PLL output clock PLL output clock disable PLL output clock enable don't care if PLL_AUTO = 1 When HIGH, the internal clocks (for logic, ADC, and DACs) are directly controlled by the pin XIN. BYP_PLL acts both on external multiplexers and on internal PLL bypass. When PLL initialization is automatic (PLL_AUTO = 1), BYP_PLL is not considered. 0 1* X 4 3 DIRECTO DIRECTI R/W R/W 0* 0* internal clocks are controlled by PLL clock internal clocks are controlled by pin XIN don't care if PLL_AUTO = 1 When DIRECTI is set to logic 1, the pre-divider is bypassed. If DIRECTO is equal to logic 1, then it is the post-divider, which is bypassed. Please see Table 59 for further details. reserved, must be set to logic 00 Put the PLL in Power-down mode if equal to logic 1. When PLL initialization is automatic (PLL_AUTO = 1), PD_PLL is not considered. 0 1* X PLL active PLL Power-down mode don't care if PLL_AUTO = 1 2 and 1 0 PD_PLL R/W R/W 00 Table 59. Truth table for PLL output clock frequency Legend: * = default value. DIRECTI 1 1 DIRECTO 1 0 PLL output clock frequency[1] fclk(o)(PLL) = fVCO = fi x 2 x M f VCO fi x M f clk(o)(PLL) = ------------ = --------------P 2xP fi x 2 x M f clk(o)(PLL) = f VCO = ------------------------N f VCO fi x M f clk(o)(PLL) = ------------ = --------------NxP 2xP 0 1 0* 0* [1] For description of M, N and P see Table 60. For optimum performances, the following relations must be respected: * 275 MHz fVCO 550 MHz * 4 kHz fi 150 MHz if DIRECTI = 1, else 4 kHz fi / N 150 MHz TDA8295_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 4 February 2008 47 of 77 NXP Semiconductors TDA8295 Digital global standard low IF demodulator for analog TV and FM radio Table 60. PLL_REG07, PLL_REG08, PLL_REG09 and PLL_REG10 register (address 3Fh to 42h) bit description Legend: * = default value. Address Register 3Fh 40h 41h Bit Symbol Access Value Description R/W R/W 00h 1Ah* 01h* 0 000 01h* not used reserved, must be set to 00h It programs the M parameter (M = MSEL + 1). M is the PLL feedback-divider. It programs the N parameter (N = NSEL + 1). N is the PLL pre-divider. reserved, must be set to logic 0 reserved, must be set to logic 000 It programs the P parameter (P = PSEL + 1). P is the PLL post-divider. PLL_REG07 7 6 to 0 - PLL_REG08 7 to 0 MSEL[7:0] R/W PLL_REG09 7 to 1 NSEL[6:0] R/W 0 R/W R/W 42h PLL_REG10 7 to 5 - 4 to 0 PSEL[4:0] R/W Table 61. XTALOSC_CTL register (address 43h) bit description Legend: * = default value. Bit 7 to 3 2 Symbol Access Value Description HF R/W R/W 0* 1 1 and 0 R/W 00 not used With HF, the transconductance of the oscillator gain stage can be set. For fXIN > 20 MHz, HF should be set to logic 1. recommended for standard application (16 MHz) recommended if fXIN > 20 MHz reserved, must be set to logic 00 TDA8295_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 4 February 2008 48 of 77 NXP Semiconductors TDA8295 Digital global standard low IF demodulator for analog TV and FM radio 9.3.20 GPIOs In the TDA8295, three general purpose input/outputs are implemented. Table 62. GPIOREG_0 register (address 44h) bit description Legend: * = default value. Bit Symbol Access Value R/W 0000 0001* 0011 0100 to 1011 XXXX Description It determines how the general purpose pin GPIO1 is configured. The GPIO1 pin is in Input mode. The input value is stored in GP1_VAL. The GPIO1 pin is in Open-drain mode. The output value is determined by GP1_VAL. The GPIO1 pin is in Output mode. The PLL output clock divided by two is delivered. The GPIO1 pin is in Output mode. HVPLL signals are delivered. The output is a one bit signal of HVPLL_BUS[7:0] according to Table 64. Don't care if I2CSW_EN = 1. Then the pad is configured as I2C-bus feed-through like described in Table 63. It determines how the general purpose pin GPIO0 is configured. 0000 0001* 0011 0100 to 1011 The GPIO0 pin is in Input mode. The input value is stored in GP0_VAL. The GPIO0 pin is in Open-drain mode. The output value is determined by GP0_VAL. The GPIO0 pin is in Output mode. The PLL output clock divided by two is delivered. The GPIO0 pin is in Output mode. HVPLL signals are delivered. The output is a one bit signal of HVPLL_BUS[7:0] according to Table 64. 7 to 4 GP1_CF[3:0] 3 to 0 GP0_CF[3:0] R/W Table 63. GPIOREG_1 register (address 45h) bit description Legend: * = default value. Bit 7 6 Symbol I2CSW_EN I2CSW_ON Access Value R/W R/W 0* 0* Description When I2CSW_EN = 1, GPIO1 and GPIO2 are configured as an I2C-bus feed-through independently of the GP1_CF and GP2_CF value. When I2CSW_ON = 0, the feed-through switch is open, and GPIO1 and GPIO2 are in 3-state. When the switch is closed (I2CSW_ON = 1), the I2C-bus clock and data signals (SCL and SDA) are available on the GPIO1 and GPIO2 pins. not used 5 and 4 - R/W - TDA8295_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 4 February 2008 49 of 77 NXP Semiconductors TDA8295 Digital global standard low IF demodulator for analog TV and FM radio Table 63. GPIOREG_1 register (address 45h) bit description ...continued Legend: * = default value. Bit 3 to 0 Symbol Access Value Description It determines how the general purpose pin GPIO2 is configured. 0000 0001* 0011 0100 to 1011 XXXX The GPIO2 pin is in Input mode. The input value is stored in GP2_VAL. The GPIO2 pin is in Open-drain mode. The output value is determined by GP2_VAL. The GPIO2 pin is in Output mode. The PLL output clock divided by two is delivered. The GPIO2 pin is in Output mode. HVPLL signals are delivered. The output is a one bit signal of HVPLL_BUS[7:0] according to Table 64. Don't care if I2CSW_EN = 1. Then the pad is configured as I2C-bus feed-through. GP2_CF[3:0] R/W Table 64. HVPLL bus mapping Signal V_SYNC H_SYNC NOISE_DET MAC_DET FIDT V_LOCK F_H_LOCK N_H_LOCK HVPLL_BUS bit HVPLL_BUS[7] HVPLL_BUS[6] HVPLL_BUS[5] HVPLL_BUS[4] HVPLL_BUS[3] HVPLL_BUS[2] HVPLL_BUS[1] HVPLL_BUS[0] Table 65. GPIOREG_2 register (address 46h) bit description Legend: * = default value. Bit 7 6 5 2 Symbol Access Value 0* 0* 0* 1* Description With CLK_INV_GPx, the output clock polarity can be changed. This is only useful when GPx_CF[3:0] = 0011. not used GP2_VAL controls the value of the pin GPIO2 when GP2_CF[3:0] = 0001. When GP2_CF[3:0] = 0000, GPIO2 is an input pin which value can be read through the I2C-bus stored in GP2_VAL. GP1_VAL controls the value of the pin GPIO1 when GP1_CF[3:0] = 0001. When GP1_CF[3:0] = 0000, GPIO1 is an input pin which value can be read through the I2C-bus stored in GP1_VAL. GP0_VAL controls the value of the pin GPIO0 when GP0_CF[3:0] = 0001. When GP0_CF[3:0] = 0000, GPIO0 is an input pin which value can be read through the I2C-bus stored in GP0_VAL. CLK_INV_GP2 R/W CLK_INV_GP1 R/W CLK_INV_GP0 R/W R/W R/W GP2_VAL 4 and 3 - 1 GP1_VAL R/W 1* 0 GP0_VAL R/W 1* TDA8295_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 4 February 2008 50 of 77 NXP Semiconductors TDA8295 Digital global standard low IF demodulator for analog TV and FM radio 10. Limiting values Table 66. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1][2] Symbol VDDDC(1V2) VDDA(ADC)(3V3) VDDA(PLL)(1V2) VDDA(OSC)(1V2) Vi Parameter core digital supply voltage (1.2 V) ADC analog supply voltage (3.3 V) PLL analog supply voltage (1.2 V) oscillator analog supply voltage (1.2 V) input voltage pins IF_POS and IF_NEG digital input pins (5 V tolerant) pin XIN Tlead Ptot Tstg Tj Tamb Vesd lead temperature total power dissipation storage temperature junction temperature ambient temperature electrostatic discharge voltage pins SDA, SCL, SADDR0 and SADDR1; machine model all other pins; machine model [1] [2] [3] [4] [3] Conditions Min -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -40 0 - Max +3.32 +5.63 +3.32 +3.32 +5.63 +7.5 +4.0 300 0.5 +125 125 70 150 200 Unit V V V V V V V C W C C C V V Tamb = 70 C [4] Stresses above the absolute maximum ratings may cause permanent damage to the device. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. The maximum allowed ambient temperature Tamb depends on the assembly condition of the package and especially on the design of the PCB. The application mounting must be done in such a way that the maximum junction temperature Tj(max) is never exceeded. Class A according to EIA/JESD22-A115. Class B according to EIA/JESD22-A115. 11. Thermal characteristics Table 67. Symbol Rth(j-a) Thermal characteristics Parameter thermal resistance from junction to ambient Conditions in still air Typ 33 Unit K/W The thermal resistance depends strongly on the nature of the PCB used in the application and on its design. The thermal resistance given in Table 67 corresponds to the value that can be measured on a multilayer PCB (4 layers) as defined by EIA/JESD51-2. This value is given for information only. The junction temperature influences strongly the reliability of an IC. The PCB used in the application contributes on a large part to the overall thermal characteristic. It must therefore be designed to insure that the junction temperature of the IC never exceeds Tj(max) = 125 C at the maximum ambient temperature. The IC has to be soldered to ground with its die-attached paddle. Plenty of vias are recommended to remove the heat. TDA8295_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 4 February 2008 51 of 77 NXP Semiconductors TDA8295 Digital global standard low IF demodulator for analog TV and FM radio 12. Characteristics Table 68. Characteristics Power supplies 3.3 V, 1.2 V; Tamb = 25 C; PC / SC1 for L and M = 10 dB, all others 13 dB; residual picture carrier for L = 3 %, all others 10 %; FM/AM modulation = 54 %, 1 kHz modulation frequency; measured in application PCB (see Figure 12) with 16 MHz crystal frequency, loaded with 75 (CVBS) and 1 k (SSIF/audio). Values are meant for `easy programming' settings (recommended) except internal mono audio and IF demodulation. The low IF spectrum is delivered by a professional downconverter. Symbol Power supply VDD(1V2) VDD(3V3) IDD(tot)(1V2) IDD(tot)(3V3) Ptot supply voltage (1.2 V) supply voltage (3.3 V) total supply current (1.2 V) total supply current (3.3 V) total power dissipation default settings; 75 drive; fs = 54 MHz at ADC; including DAC loads; RRSET = 1 k Power-save mode; fs = 54 MHz at ADC; including DAC loads; RRSET = 2 k; see Section 13.6 Standby mode Digital I/Os VIH HIGH-level input voltage all inputs (except pin XIN); including voltage on outputs in 3-state mode all inputs (except pin XIN); including voltage on outputs in 3-state mode source current 4 mA sink current 4 mA 0.7 x VDD(3V3) 6.0 V [1] [1] Parameter Conditions digital and analog digital and analog Min 1.08 2.97 - Typ 1.2 3.3 28 125 434 Max Unit 1.32 V 3.63 V 33 136 490 mA mA mW [2] - 324 369 mW - 7 10 mW VIL LOW-level input voltage - - 0.8 V VOH VOL Ci Master clock fclk(o)(PLL) f/fclk HIGH-level output voltage LOW-level output voltage input capacitance PLL output clock frequency relative frequency deviation from clock frequency external clock frequency RMS input voltage rising slew rate cycle-to-cycle jitter time input capacitance crystal frequency relative crystal frequency variation crystal ambient temperature VDD(3V3) - 0.4 [3] 0.4 5 - V V pF MHz 108 - - 200 10-6 Reference frequency in Slave mode fclk(ext) Vi(RMS) SRr tjit(cc) Ci fxtal fxtal/fxtal Tamb(xtal) TDA8295_1 AC coupled external clock RMS value on pin XIN 200 30 temperature, ageing and spreading 0 16 250 12.5 3 16 - - MHz mV mV/ns ps pF MHz Reference frequency in Oscillator mode (with a crystal) 200 10-6 70 C (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 4 February 2008 52 of 77 NXP Semiconductors TDA8295 Digital global standard low IF demodulator for analog TV and FM radio Table 68. Characteristics ...continued Power supplies 3.3 V, 1.2 V; Tamb = 25 C; PC / SC1 for L and M = 10 dB, all others 13 dB; residual picture carrier for L = 3 %, all others 10 %; FM/AM modulation = 54 %, 1 kHz modulation frequency; measured in application PCB (see Figure 12) with 16 MHz crystal frequency, loaded with 75 (CVBS) and 1 k (SSIF/audio). Values are meant for `easy programming' settings (recommended) except internal mono audio and IF demodulation. The low IF spectrum is delivered by a professional downconverter. Symbol IF input Vi(p-p) Ri(dif) Ci(dif) Vi peak-to-peak input voltage differential input resistance differential input capacitance input voltage operational input related to ADC full scale; all standards; sum of all signals PC / SC1 M/N standard B standard G/H standard I standard DK and L standard L-accent standard FM radio IF selectivity sup(stpb) stop-band suppression Hilbert filter stop-band decimation filter stop-band notch for NSC (NPC for L-accent standard) Carrier recovery FPLL B-3dB(cl) closed-loop -3 dB bandwidth ultrawide superwide wide medium narrow fpullin mover(PC) fstep(AFC) BT(tot) sup(stpb) pull-in frequency range picture carrier overmodulation index AFC step frequency total transition bandwidth stop-band suppression black for L/L-accent standard; flat field white else 128 steps Nyquist filter; all standards Nyquist filter; all standards video low-pass filter (M/N, B/G/H, I, D/K, L/L-accent standard) [5] [5] [4] Parameter Conditions for full-scale ADC input (0 dBFS) Min 1.8 10 -3 Typ 2.0 15 2 -3 Max Unit 2.2 3 -3 V k pF dBFS fi input frequency -60 -40 -40 5.75 / 1.25 6.75 / 1.25 7.75 / 2.25 7.75 / 1.75 7.75 / 1.25 1.25 / 7.75 1.25 - MHz MHz MHz MHz MHz MHz MHz dB dB dB 280 130 60 30 15 830 115 13 1 -60 - 280 130 60 30 15 830 117 1 -60 280 130 60 30 15 1 - kHz kHz kHz kHz kHz % kHz MHz dB dB 830 kHz IF demodulation (video equalizer in Flat mode) TDA8295_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 4 February 2008 53 of 77 NXP Semiconductors TDA8295 Digital global standard low IF demodulator for analog TV and FM radio Table 68. Characteristics ...continued Power supplies 3.3 V, 1.2 V; Tamb = 25 C; PC / SC1 for L and M = 10 dB, all others 13 dB; residual picture carrier for L = 3 %, all others 10 %; FM/AM modulation = 54 %, 1 kHz modulation frequency; measured in application PCB (see Figure 12) with 16 MHz crystal frequency, loaded with 75 (CVBS) and 1 k (SSIF/audio). Values are meant for `easy programming' settings (recommended) except internal mono audio and IF demodulation. The low IF spectrum is delivered by a professional downconverter. Symbol Bvideo(-1dB) Parameter -1 dB video bandwidth Conditions M/N standard B/G/H, I, D/K, L/L-accent standard tripple(GDE) group delay equalizer ripple time peak value for B/G/H half, D/K half, I flat, M (FCC) full, L/L-accent full standard negative modulation (all standards except L/L-accent) positive modulation (L/L-accent standard) tresp response time 20 dB level change; video settled within 3 dB negative modulation (all standards except L/L-accent) positive modulation (L/L-accent standard) GAGC tresp AGC gain range response time at 60 dBV (RMS) PC input; 20 dB level change; video settled within 3 dB with TDA8275A; positive modulation with TDA8275A; negative modulation with TDA1827x; positive modulation with TDA1827x; negative modulation f-3dB(lpf) low-pass filter -3 dB frequency IF AGC postfilter [7] [6] Min - Typ 3.9 4.9 20 Max Unit 40 MHz MHz ns Digital IF AGC (internal loop) B-3dB(cl) closed-loop -3 dB bandwidth 400 0.2 Hz Hz 3 3 3 ms 100 -20 100 - 100 +48 ms dB Tuner IF AGC (external loop) 0.9 4000 500 3000 600 1.0 1.1 ms ms ms ms kHz TDA8295_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 4 February 2008 54 of 77 NXP Semiconductors TDA8295 Digital global standard low IF demodulator for analog TV and FM radio Table 68. Characteristics ...continued Power supplies 3.3 V, 1.2 V; Tamb = 25 C; PC / SC1 for L and M = 10 dB, all others 13 dB; residual picture carrier for L = 3 %, all others 10 %; FM/AM modulation = 54 %, 1 kHz modulation frequency; measured in application PCB (see Figure 12) with 16 MHz crystal frequency, loaded with 75 (CVBS) and 1 k (SSIF/audio). Values are meant for `easy programming' settings (recommended) except internal mono audio and IF demodulation. The low IF spectrum is delivered by a professional downconverter. Symbol CVBS output Vo(p-p) peak-to-peak output voltage negative PC modulation (all standards except L/L-accent); 75 DC load; sync-white modulation 65 % 90 % (nominal) 115 % positive PC modulation (L/L-accent standard); 75 DC load; sync-white modulation 65 % 97 % (nominal) 115 % Bvideo(-3dB) -3 dB video bandwidth overall video response; CVBS equalizer flat all standards except M/N M/N standard resp(f) frequency response video equalizer; 8 equally spaced settings; value at 3.9 MHz 4.8 3.9 -5 4.85 4.05 MHz MHz 0.8 0.7 1.0 1.0 0.9 1.2 1.2 V V V 0.8 0.7 1.0 1.0 0.9 1.2 1.2 V V V Parameter Conditions Min Typ Max Unit +4.5 dB Gdif dif differential gain differential phase "ITU-T J.63 line 330" "ITU-T J.63 line 330" - 1.5 1.5 1 3 3 2 % deg % Vstlt/VCVBS(p-p) synchronization tilt voltage to peak-to-peak CVBS voltage ratio Vftlt/VCVBS(p-p) frame tilt voltage to peak-to-peak CVBS voltage ratio Vtro/Vtro IM(blue) relative transient response overshoot voltage variation all standards except L/L-accent L/L-accent standard in peak white AGC detection 2T pulse [8] - 1 1 2 3 5 5 % % % intermodulation suppression carrier levels related to PC (blue) sync; PC = -3.2 dB; CC = -19.2 dB; SC = -13 dB 1.1 MHz (related to black-to-white in RMS, equals CC + 3.6 dB) 3.3 MHz (related to CC) 64 dB - 75 - dB TDA8295_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 4 February 2008 55 of 77 NXP Semiconductors TDA8295 Digital global standard low IF demodulator for analog TV and FM radio Table 68. Characteristics ...continued Power supplies 3.3 V, 1.2 V; Tamb = 25 C; PC / SC1 for L and M = 10 dB, all others 13 dB; residual picture carrier for L = 3 %, all others 10 %; FM/AM modulation = 54 %, 1 kHz modulation frequency; measured in application PCB (see Figure 12) with 16 MHz crystal frequency, loaded with 75 (CVBS) and 1 k (SSIF/audio). Values are meant for `easy programming' settings (recommended) except internal mono audio and IF demodulation. The low IF spectrum is delivered by a professional downconverter. Symbol IM(yellow) Parameter Conditions Min Typ Max Unit intermodulation suppression carrier levels related to PC (yellow) sync; PC = -10 dB; CC = -19.2 dB; SC = -13 dB 1.1 MHz (related to black-to-white in RMS, equals CC + 3.6 dB) 3.3 MHz (related to CC) (S/N)w weighted signal-to-noise ratio all standards; unified weighting filter ("ITU-T J.61"); PC at -6 dBFS 69 dB 58 81 62 - dB dB TDA8295_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 4 February 2008 56 of 77 NXP Semiconductors TDA8295 Digital global standard low IF demodulator for analog TV and FM radio Table 68. Characteristics ...continued Power supplies 3.3 V, 1.2 V; Tamb = 25 C; PC / SC1 for L and M = 10 dB, all others 13 dB; residual picture carrier for L = 3 %, all others 10 %; FM/AM modulation = 54 %, 1 kHz modulation frequency; measured in application PCB (see Figure 12) with 16 MHz crystal frequency, loaded with 75 (CVBS) and 1 k (SSIF/audio). Values are meant for `easy programming' settings (recommended) except internal mono audio and IF demodulation. The low IF spectrum is delivered by a professional downconverter. Symbol PSRR Parameter power supply rejection ratio Conditions fripple = 70 Hz; 100 mV (p-p); video signal: gray; level: 50 %; TDA8295 stand alone; input level: 60 dBV (RMS) PC positive video modulation; L standard; 1.2 V positive video modulation; L standard; 3.3 V negative video modulation; B standard; 1.2 V negative video modulation; B standard; 3.3 V fripple = 70 Hz; 100 mV (p-p); video signal: gray; level: 50 %; together with TDA8275A; input level: 60 dBV (RMS) PC positive video modulation; L standard; 1.2 V positive video modulation; L standard; 3.3 V negative video modulation; B standard; 1.2 V negative video modulation; B standard; 3.3 V fripple = 70 Hz; 100 mV (p-p); video signal: gray; level: 50 %; together with TDA1827x; input level: 60 dBV (RMS) PC positive video modulation; L standard; 1.2 V positive video modulation; L standard; 3.3 V negative video modulation; B standard; 1.2 V negative video modulation; B standard; 3.3 V sup(f)L(unw) unwanted leakage frequency suppression 4.8 MHz video modulation; related to black-to-white in 10 MHz to 200 MHz band [9] [9] [9] [9] [9] [9] Min Typ Max Unit - 52 30 51 30 - dB dB dB dB - 26 22 43 32 - dB dB dB dB - 26 22 43 32 56 - dB dB dB dB dB TDA8295_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 4 February 2008 57 of 77 NXP Semiconductors TDA8295 Digital global standard low IF demodulator for analog TV and FM radio Table 68. Characteristics ...continued Power supplies 3.3 V, 1.2 V; Tamb = 25 C; PC / SC1 for L and M = 10 dB, all others 13 dB; residual picture carrier for L = 3 %, all others 10 %; FM/AM modulation = 54 %, 1 kHz modulation frequency; measured in application PCB (see Figure 12) with 16 MHz crystal frequency, loaded with 75 (CVBS) and 1 k (SSIF/audio). Values are meant for `easy programming' settings (recommended) except internal mono audio and IF demodulation. The low IF spectrum is delivered by a professional downconverter. Symbol fo(SSIF) Parameter SSIF output frequency Conditions SC1 or FM radio carrier M standard B/G/H standard I standard D/K/L/L-accent standard FM radio Vo(SSIF)(RMS) RMS SSIF output voltage 1 k DC or AC load; no modulation; PC / SC1 = 13 dB; scaled linearly for all other ratios all standards except B/G/H B/G/H standard FM radio (single carrier) Vo(AF)(RMS) RMS AF output voltage 1 k DC or AC load M standard; 54 % modulation degree (13.5 kHz FM deviation before pre-emphasis) B, G/H, I, D, K standard; 54 % modulation degree (27 kHz FM deviation before pre-emphasis) L/L-accent standard; AM; m = 54 % FM radio; 30 % modulation degree (22.5 kHz FM deviation before pre-emphasis) high Deviation mode (D/K standard China); FM deviation before pre-emphasis 400 kHz; sound level setting: -12 dB 125 143 165 mV 30 27 460 35 32 530 40 37 610 mV mV mV [10] Min Typ Max Unit SSIF/mono sound output 4.5 5.5 6.0 6.5 5.5 MHz MHz MHz MHz MHz 125 143 165 mV 110 56 126 65 145 75 mV mV 487 560 644 mV TDA8295_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 4 February 2008 58 of 77 NXP Semiconductors TDA8295 Digital global standard low IF demodulator for analog TV and FM radio Table 68. Characteristics ...continued Power supplies 3.3 V, 1.2 V; Tamb = 25 C; PC / SC1 for L and M = 10 dB, all others 13 dB; residual picture carrier for L = 3 %, all others 10 %; FM/AM modulation = 54 %, 1 kHz modulation frequency; measured in application PCB (see Figure 12) with 16 MHz crystal frequency, loaded with 75 (CVBS) and 1 k (SSIF/audio). Values are meant for `easy programming' settings (recommended) except internal mono audio and IF demodulation. The low IF spectrum is delivered by a professional downconverter. Symbol hr(AF) Parameter AF headroom Conditions before clipping; 1 k DC or AC load M standard; related to 25 kHz peak deviation before pre-emphasis B, G/H, I, D, K standard; related to 50 kHz peak deviation before pre-emphasis L/L-accent standard; PC / SC1 ratio for start of audio output clipping; AM; m = 100 %; related to mean SC1 FM radio; 30 % modulation degree related to 22.5 kHz peak deviation before pre-emphasis deemp de-emphasis time constant M/N standard (mono); FM radio USA B/G/H, I, D/K standard; FM radio Europe B-3dB -3 dB bandwidth audio low-pass filter L/L-accent standard M-BTSC standard THD total harmonic distortion FM; for 50 kHz deviation before pre-emphasis (25 kHz for M standard) AM; m = 80 % BAF(-3dB) AM -3 dB AF bandwidth AM suppression AM FM of FM demodulator; AM: f = 1 kHz; m = 54 % referenced to 27 kHz FM deviation 30 140 30 140 0.1 30 140 0.2 kHz kHz % 7 7 7 dB Min Typ Max Unit 7 7 7 dB 1 1 1 dB 7 7 7 dB 75 50 75 50 75 50 s s 20 40 40 0.6 27 50 46 1 - % kHz kHz dB TDA8295_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 4 February 2008 59 of 77 NXP Semiconductors TDA8295 Digital global standard low IF demodulator for analog TV and FM radio Table 68. Characteristics ...continued Power supplies 3.3 V, 1.2 V; Tamb = 25 C; PC / SC1 for L and M = 10 dB, all others 13 dB; residual picture carrier for L = 3 %, all others 10 %; FM/AM modulation = 54 %, 1 kHz modulation frequency; measured in application PCB (see Figure 12) with 16 MHz crystal frequency, loaded with 75 (CVBS) and 1 k (SSIF/audio). Values are meant for `easy programming' settings (recommended) except internal mono audio and IF demodulation. The low IF spectrum is delivered by a professional downconverter. Symbol (S/N)w(AF) Parameter AF weighted signal-to-noise ratio Conditions via internal mono sound demodulator; "ITU-R BS.468-4"; FM mode related to 27 kHz deviation before pre-emphasis; 10 % residual PC; SC1 black picture flat field white picture 6 kHz sine wave picture 250 kHz square wave picture crosshatch picture color bar picture via internal mono sound demodulator; "ITU-R BS.468-4"; AM; m = 54 %; 3 % residual PC; SC1 black picture flat field white picture color bar picture via internal mono sound demodulator; "ITU-R BS.468-4"; FM Radio mode 43 43 43 47 45 46 46 51 dB dB dB dB 54 53 52 52 52 54 58 57 56 56 56 58 dB dB dB dB dB dB Min Typ Max Unit TDA8295_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 4 February 2008 60 of 77 NXP Semiconductors TDA8295 Digital global standard low IF demodulator for analog TV and FM radio Table 68. Characteristics ...continued Power supplies 3.3 V, 1.2 V; Tamb = 25 C; PC / SC1 for L and M = 10 dB, all others 13 dB; residual picture carrier for L = 3 %, all others 10 %; FM/AM modulation = 54 %, 1 kHz modulation frequency; measured in application PCB (see Figure 12) with 16 MHz crystal frequency, loaded with 75 (CVBS) and 1 k (SSIF/audio). Values are meant for `easy programming' settings (recommended) except internal mono audio and IF demodulation. The low IF spectrum is delivered by a professional downconverter. Symbol (S/N)w(SC1) Parameter first sound carrier weighted signal-to-noise ratio Conditions via external SSIF sound demodulator in Dual mode; "ITU-R BS.468-4"; FM mode related to 27 kHz deviation before pre-emphasis; 10 % residual PC black picture flat field white picture 6 kHz sine wave picture 250 kHz square wave picture crosshatch picture color bar picture via SSIF sound demodulator; "ITU-R BS.468-4"; AM; m = 54 %; 3 % residual PC black picture flat field white picture color bar picture (S/N)w(SC2) second sound carrier weighted signal-to-noise ratio via external SSIF sound demodulator in Dual mode; "ITU-R BS.468-4"; FM mode related to 27 kHz deviation before pre-emphasis; 10 % residual PC black picture flat field white picture 6 kHz sine wave picture 250 kHz square wave picture crosshatch picture color bar picture (S/N)w weighted signal-to-noise ratio FM radio; via SSIF sound demodulator in Mono mode; "ITU-R BS.468-4" 58 58 54 46 56 57 60 62 62 58 50 60 61 64 dB dB dB dB dB dB dB 40 40 40 43 43 43 dB dB dB 60 60 54 55 54 59 64 64 58 59 58 63 dB dB dB dB dB dB Min Typ Max Unit TDA8295_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 4 February 2008 61 of 77 NXP Semiconductors TDA8295 Digital global standard low IF demodulator for analog TV and FM radio Table 68. Characteristics ...continued Power supplies 3.3 V, 1.2 V; Tamb = 25 C; PC / SC1 for L and M = 10 dB, all others 13 dB; residual picture carrier for L = 3 %, all others 10 %; FM/AM modulation = 54 %, 1 kHz modulation frequency; measured in application PCB (see Figure 12) with 16 MHz crystal frequency, loaded with 75 (CVBS) and 1 k (SSIF/audio). Values are meant for `easy programming' settings (recommended) except internal mono audio and IF demodulation. The low IF spectrum is delivered by a professional downconverter. Symbol PSRR Parameter power supply rejection ratio Conditions fripple = 70 Hz; 100 mV (p-p); video signal: gray; level: 50 %; TDA8295 stand alone FM sound; 1.2 V FM sound; 3.3 V AM sound; 1.2 V AM sound; 3.3 V fripple = 70 Hz; 100 mV (p-p); video signal: gray; level: 50 %; together with TDA8275A; input level: 60 dBV (RMS) PC FM sound; 1.2 V FM sound; 3.3 V AM sound; 1.2 V AM sound; 3.3 V fripple = 70 Hz; 100 mV (p-p); video signal: gray; level: 50 %; together with TDA1827x; input level: 60 dBV (RMS) PC FM sound; 1.2 V FM sound; 3.3 V AM sound; 1.2 V AM sound; 3.3 V sup(f)L(unw) unwanted leakage frequency suppression related to SSIF (SC1) in 10 MHz to 200 MHz band [9] [9] [9] [9] [9] [9] Min Typ Max Unit - 72 33 68 37 - dB dB dB dB - 72 33 22 22 - dB dB dB dB - 72 33 22 22 33 - dB dB dB dB dB [1] [2] [3] [4] [5] [6] [7] [8] [9] 50 % ADC current; 100 % video DAC current; 50 % sound DAC current. 50 % ADC current; 50 % video DAC current; 25 % sound DAC current. See Section 9.3.19 for PLL setting. Standard dependent located at 7.25 MHz, 8.25 MHz, 9.25 MHz, 9.75 MHz and 10.25 MHz. The pull-in range can be doubled to 1660 kHz by I2C-bus register like described in Table 16. Then the AFC read-out has 256 steps. To counteract a fast IF level reduction, the digital IF AGC loop has a speed-up circuit for positive video modulation. In the ordinary system application, this slow response is counteracted by the fast digital IF AGC loop. ADC clipping is practically avoided by fast-attack AGC characteristic. HAD: 250 ns for M standard, 200 ns for others. The values given are measured with an IF AGC time constant of 5 Hz. For that, capacitor C7 in Figure 12 must be chosen 220 nF instead of 2.2 nF. Doing so, the PSRR on 3.3 V together with the tuner can be improved. [10] SC2 is not listed, but supported for all world standards. TDA8295_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 4 February 2008 62 of 77 NXP Semiconductors TDA8295 Digital global standard low IF demodulator for analog TV and FM radio 13. Application information 13.1 Typical application I2C-bus SDA_O SCL_O V-sync VSYNC SDA SCL V_IOUTN V_IOUTP CVBS I2C-bus SAA71xx TDA8275A TDA1827x (TUNER ICs) IF_POS low IF signal IF_NEG TDA8295 S_IOUTP SSIF (AUDIO AND VIDEO DECODER) IF_AGC tuner IF AGC XIN reference frequency RSET S_IOUTN processed audio and video 001aah420 Fig 11. Typical application of TDA8295 TDA8295_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 4 February 2008 63 of 77 xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x Product data sheet Rev. 01 -- 4 February 2008 (c) NXP B.V. 2008. All rights reserved. TDA8295_1 NXP Semiconductors 13.2 Detailed application diagram 1.2 V R6 10 1.2 V R5 10 1.2 V R8 2.2 3.3 V R7 10 3.3 V R9 10 3.3 V R10 1 3.3 V R11 1 C10 C9 220 nF C12 220 nF F1 C11 470 nF C13 470 nF F2 C14 470 nF F3 C16 470 nF AGND 220 nF DGND AGND DGND VDDA(PLL)(1V2) DGND DGND DGND DGND AGND AGND AGND VDDA(DAC2)(3V3) VDDA(DAC1)(3V3) AGND R12 1 k AGND VDDD(ADC)(3V3) VDDA(ADC)(3V3) VDDDR(3V3) VDDD1(1V2) VDDD2(1V2) VSSA(ADC) VSSA(DAC) VSSA(PLL) VSSDR VSSD1 VSSD2 RSET Digital global standard low IF demodulator for analog TV and FM radio 40 XOUT reference frequency to TDA8275A or TDA1827x low IF 1 nF R1 150 k C7 2.2 nF C2 100 pF C3 1 nF C4 7 10 5 4 25 35 26 34 39 3 12 18 15 11 13 14 V_IOUTN V_IOUTP R13 39 R14 75 AGND CVBS C5 470 pF 9 8 XIN IF_POS to SCART or processor 1 IC1 TDA8295 IF_NEG 2 AGND/ DGND AGND AGND S_IOUTP SSIF or 17 AUDIO R15 75 C6 270 pF IF_AGC 37 29 SDA 28 SCL 19 SADDR0 20 SADDR1 21 RST_N 33 GPIO0/VSYNC 32 GPIO1/SCL_O 31 GPIO2/SDA_O 6 i.c. 38 i.c. 36 i.c. 24 TMS 30 TRST_N 27 TCK 23 TDI 22 TDO 16 AGND AGND S_IOUTN R16 AGND 75 AGND DGND DGND DGND DGND DGND DGND DGND R3 100 R4 100 R2 3.3 V 2.2 k C8 100 nF 3.3 V supply 3.3 V C15 47 F 1.2 V supply 1.2 V C1 47 F I2C-bus DGND DGND DGND AGND AGND 001aah421 TDA8295 F1, F2, F3: BLM18AG102SN1 ferrite bead Preferred components: SMD R1 has to be placed near to TDA8295 pin 37 and SMD C7 near to TDA8275A or TDA1827x 64 of 77 Fig 12. Detailed application diagram of TDA8295 NXP Semiconductors TDA8295 Digital global standard low IF demodulator for analog TV and FM radio 13.3 DAC connection This DAC has a differential current output capable of driving a doubly terminated 75 transmission line without external buffers. But it can also be used in single-ended applications. In that case both outputs still need proper termination. The off-chip resistive load must be connected to ground. With the B_DA_V and B_DA_S coarse output level adjustment registers, the output current can be increased (linearly) up to two times. However, the maximum output voltage at both V_IOUTP, V_IOUTN and S_IOUTP, S_IOUTN output nodes still is 1.5 V. DNL and INL increase when the external biasing resistor is increased. When higher load resistances are used, distortion will increase linearly. About 12 dB increase in harmonic distortion is expected at 150 . Several measures can be taken in order to reach good performance. Decouple the VDDA(DAC1)(3V3) and the VDDA(DAC2)(3V3) supplies with at least 100 nF. Place the external bias resistor close to the chip. Do not add decoupling capacitance to pin RSET. The following relation gives the value of the full-scale current IFS in function of the bias resistance value, FineControl (B_REF) and CoarseControl (B_DA_V or B_DA_S): 1.216 100 1 64 + CoarseControl I FS = ------------ x ------------------------------------------- x -- x ----------------------------------------------- x 64 -RSET 100 - FineControl 5 48 -7 FineControl +7 0 CoarseControl 63 For programming of FineControl (B_REF) see Table 55, for CoarseControl signals B_DA_V see Table 53, for B_DA_S see Table 54. (1) 13.4 ADC connection The input signals of the ADC (IF_POS and IF_NEG) can be either AC coupled by means of two capacitors or connected directly to the inputs (DC coupled). This selection is done by programming of DCIN, see Table 51. In case of AC coupling, DCIN should be set to logic 0, which enables two resistive dividers between VDDA(ADC)(3V3) and VSSD1 take care of the correct DC biasing of the input signals. In case only a single-ended input signal is available, this signal should be connected to the IF_POS input by means of a coupling capacitor whereas the IF_NEG input should be connected to ground using a similar capacitor. In case the input signal is DC coupled, the input resistor network can be switched off by setting the DCIN bit to logic 1. When using the ADC in this mode, the Common mode level of the input signals should be at 0.5 x VDDA(ADC)(3V3). In case of single-ended operation, the input signal should be connected directly to the IF_POS input and the IF_NEG input should be connected to a voltage equal to the Common mode level of the input signal (0.5 x VDDA(ADC)(3V3)). The peak-to-peak input range can be set to 1 V (p-p) or 2 V (p-p) by programming of GAINSET (see Table 51). With a differential input the performances of the ADC are slightly better with GAINSET = 0 whereas with a single-ended input they are slightly better with GAINSET = 1. TDA8295_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 4 February 2008 65 of 77 NXP Semiconductors TDA8295 Digital global standard low IF demodulator for analog TV and FM radio 13.5 Reset operation 13.5.1 Hardware reset minimum width at LOW is 4 x TXIN RST_N XIN TXIN the TDA8295 enters immediately in its reset mode TDA8295 normal operation starts after 4 falling edges of XIN 001aah362 Fig 13. Hardware reset operation After a hardware reset, the registers are set to default (power-on reset values) according to Table 10. M/N standard is the default standard. 13.5.2 Software reset A software reset can be done each time something has been programmed. The software reset does not affect the content of the registers but clears the flip-flops in the design. For the activation of the software reset see Table 49 bit CLB. 13.6 Application hints * In case GPIO1 and GPIO2 are configured as I2C-bus feed-through, a capacitor C = 33 pF to GND must be added at pin 32 (GPIO1/SCL_O). This ensures a reliable behavior in Read mode. * The detailed application diagram (see Figure 12) shows the video DAC connection driving a 75 DC load and the sound DAC driving > 1 k AC/DC load. Power-save mode: In order to reduce power consumption, the video DAC can be run with half current and the sound DAC with a quarter current by changing RSET (R12 in Figure 12) to 2 k. This is possible, if the audio/video processor is rather high-ohmic (> 1 k). The following components in Figure 12 have to be replaced then: R13 = 75 ; R15 and R16 = 150 ; C5 = 220 pF; C6 = 120 pF. A performance degradation is not expected in the Power-save mode. The TDA8295 has been designed in such a way, that a simple upgrade of the predecessor TDA8290 is possible: 1. Change the 1.8 V power supply to 1.2 V. This can be done easily with a variable voltage regulator, where the sense pin is grounded. This delivers the band gap voltage of 1.25 V to the output. Or take a fixed regulator. 2. The RSET resistor (R12 in Figure 12) has to be decreased by 20 % in order to make the DAC output swing higher (1.5 V instead of 1.25 V). 3. Pin 6 and pin 36 (both internally connected pins) can still stay connected to the 1.2 V power supply, as done in the PCBs for the predecessor TDA8290 without harm. However, take grounds for new designs, because they are more easily accessible on a PCB. TDA8295_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 4 February 2008 66 of 77 NXP Semiconductors TDA8295 Digital global standard low IF demodulator for analog TV and FM radio 13.7 Crystal connection The typical crystal frequency value is 16 MHz. The values of the passive components depend on crystal manufacturer. The oscillator can be set in two configurations depending on the origin of the crystal. Figure 14 describes the case of an crystal shared with the tuner and the TDA8295 (Slave mode), Figure 15 the case of an crystal dedicated to the TDA8295 (Oscillator mode). TDA8295 TDA8295 Rbias Rbias XIN XIN 100 nF C1 XOUT XTAL XOUT C2 clock signal from tuner n.c. 001aah363 GND GND 001aah364 Slave mode Oscillator mode Fig 14. Reference clock application Fig 15. Oscillator application In Oscillator mode, only a crystal and the load capacitances C1 and C2 need to be connected externally since the feedback resistance is integrated on chip. In this mode the oscillator gain stage can have a normal or large transconductance, determined by the HF bit (see also Table 61). A large transconductance is required for higher oscillation frequencies, higher series resistance of the crystal and higher external load capacitors. For an accurate time reference it is advised to use the load capacitors as specified in Table 69. CL is the typical load capacitance of the crystal and is usually specified by the crystal manufacturer. Table 69. Crystal parameters together with external components Crystal load capacitance CL(xtal) (pF) 10 20 30 5 MHz to 10 MHz 10 20 30 10 MHz to 15 MHz 15 MHz to 20 MHz 10 20 10 Crystal series resistance Rs(xtal) () < 300 < 300 < 300 < 300 < 200 < 100 < 160 < 60 < 80 External load capacitors C1 (pF) C2 (pF) Fundamental oscillation frequency Bit HF = 0 1 MHz to 5 MHz 18 39 56 18 39 56 18 39 18 18 39 56 18 39 56 18 39 18 TDA8295_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 4 February 2008 67 of 77 NXP Semiconductors TDA8295 Digital global standard low IF demodulator for analog TV and FM radio Crystal parameters together with external components ...continued Crystal load capacitance CL(xtal) (pF) 10 20 10 20 10 20 10 20 10 10 10 10 Crystal series resistance Rs(xtal) () < 200 < 120 < 180 < 100 < 160 < 80 < 130 < 60 < 120 < 100 < 80 < 60 External load capacitors C1 (pF) C2 (pF) Table 69. Fundamental oscillation frequency Bit HF = 1 10 MHz to 15 MHz 15 MHz to 20 MHz 20 MHz to 25 MHz 25 MHz to 30 MHz 30 MHz to 35 MHz 35 MHz to 40 MHz 40 MHz to 45 MHz 45 MHz to 50 MHz 18 39 18 39 18 39 18 39 18 18 18 18 18 39 18 39 18 39 18 39 18 18 18 18 14. Test information 14.1 Boundary scan interface ("IEEE Std. 1149.1") The TDA8295 implements a boundary scan architecture to allow access to, and control of, board test support features within integrated circuits through a TAP. The TAP controller is a synchronous state machine that controls the sequence of operations on the TAP circuitry when the TMS signal changes. All state transitions occur on the basis of the TMS value on the rising edge of TCK. The instruction register is a shift register based design. It decodes the test to be performed and/or the test data register to be accessed. The instructions are shifted into the register through the TDI and are latched as the current instruction at the completion of the shifting process. The TDA8295 boundary scan architecture includes: a TAP controller, a scannable instruction register and three scannable test data registers: a boundary scan register, a device ID register, and a bypass register. The supported instructions are: EXTEST, IDCODE, SAMPLE, INTEST, CLAMP, HIGHZ and BYPASS. The boundary scan register is composed of 16 cells (see Table 70). Each cell is associated either to an input pad, an output pad, a bidirectional pad or to the bidirectional or 3-state command itself. All cells are of `observe and control' type. The device ID register is a 32-bit identification register that is included in the scan register itself and contains the ID number. It is a fixed value that identifies the chip. TDA8295_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 4 February 2008 68 of 77 NXP Semiconductors TDA8295 Digital global standard low IF demodulator for analog TV and FM radio ID number structure is: ID version [3:0] = 1h ID part number [15:0] = 224Ch ID manufacturer [11:1] = 015h ID mandatory [0] = 1h IDCODE [31:0] = 1224 C02Bh When the boundary scan function is not used, please connect the four dedicated input pins (TRST_N, TCK, TDI and TMS) to GND. BOUNDARY SCAN REGISTER DEVICE ID REGISTER MUX BYPASS REGISTER control MUX FF TDI INSTRUCTION DECODE TDO INSTRUCTION REGISTER TMS TCK TRST_N TEST ACCESS PORT CONTROLLER select 3-state enable 001aac078 Fig 16. Boundary scan block diagram TDA8295_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 4 February 2008 69 of 77 NXP Semiconductors TDA8295 Digital global standard low IF demodulator for analog TV and FM radio Boundary scan register list Chain position [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] Pad type Bidir Ctrl Bidir Ctrl Bidir Ctrl Bidir Ctrl Bidir Ctrl input input Ctrl Bidir Ctrl Bidir Scan type control/observe control/observe control/observe control/observe control/observe control/observe control/observe control/observe control/observe control/observe control/observe control/observe control/observe control/observe control/observe control/observe Control signal U1.vagc_cmd U1.vagc_cmd U1.gpio0_cmd U1.gpio0_cmd U1.gpio1_cmd U1.gpio1_cmd U1.gpio2_cmd U1.gpio2_cmd U1.sda_cmd U1.sda_cmd U1.saddr1_cmd U1.saddr1_cmd U0.saddr1_cmd U0.saddr1_cmd Table 70. Pad signal IF_AGC GPIO0 GPIO1 GPIO2 SDA SCL RST_N SADDR1 SADDR0 Table 71. Symbol Tcy tsu th td(TDO) Boundary scan electrical characteristics Parameter cycle time set-up time hold time delay time on pin TDO Conditions TCK TDI and TMS TDI and TMS on 50 pF Min 25 0 4 Typ Max 12 Unit ns ns ns ns Tcy TCK tsu TDI, TMS td TDO 001aac079 th Fig 17. Boundary scan timing diagram TDA8295_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 4 February 2008 70 of 77 NXP Semiconductors TDA8295 Digital global standard low IF demodulator for analog TV and FM radio 15. Package outline HVQFN40: plastic thermal enhanced very thin quad flat package; no leads; 40 terminals; body 6 x 6 x 0.85 mm SOT618-1 D B A terminal 1 index area E A A1 c detail X e1 e 11 L 10 21 e 1/2 e C b 20 vMCAB wMC y1 C y Eh 1/2 e e2 1 terminal 1 index area 30 40 Dh 0 2.5 scale E(1) 6.1 5.9 Eh 4.25 3.95 e 0.5 e1 4.5 e2 4.5 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1 5 mm 31 X DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.30 0.18 c 0.2 D(1) 6.1 5.9 Dh 4.25 3.95 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT618-1 REFERENCES IEC --JEDEC MO-220 JEITA --EUROPEAN PROJECTION ISSUE DATE 01-08-08 02-10-22 Fig 18. Package outline SOT618-1 (HVQFN40) TDA8295_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 4 February 2008 71 of 77 NXP Semiconductors TDA8295 Digital global standard low IF demodulator for analog TV and FM radio 16. Soldering This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description". 16.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 16.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: * Through-hole components * Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: * * * * * * Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus PbSn soldering 16.3 Wave soldering Key characteristics in wave soldering are: * Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave * Solder bath specifications, including temperature and impurities TDA8295_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 4 February 2008 72 of 77 NXP Semiconductors TDA8295 Digital global standard low IF demodulator for analog TV and FM radio 16.4 Reflow soldering Key characteristics in reflow soldering are: * Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 19) than a PbSn process, thus reducing the process window * Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board * Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 72 and 73 Table 72. SnPb eutectic process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 2.5 2.5 Table 73. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 350 220 220 Package thickness (mm) Package thickness (mm) Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 19. TDA8295_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 4 February 2008 73 of 77 NXP Semiconductors TDA8295 Digital global standard low IF demodulator for analog TV and FM radio temperature maximum peak temperature = MSL limit, damage level minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 19. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description". 17. Abbreviations Table 74. Acronym ADC AFC AGC CC CMOS CORDIC CVBS DAC DTO DVD FIR FLL FPLL FS GPIO H/V HAD IC ICFM TDA8295_1 Abbreviations Description Analog-to-Digital Converter Automatic Frequency Control Automatic Gain Control Color Carrier Complementary Metal-Oxide Semiconductor COordinate Rotation DIgital Computer Color Video Blanking Signal Digital-to-Analog Converter Digitally Tuned Oscillator Digital Versatile Disc Finite Impulse Response Frequency-Locked Loop Frequency Phase-Locked Loop Full Scale General Purpose Input Output Horizontal and Vertical Half Amplitude Duration Integrated Circuit Incidental Carrier Frequency Modulation (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 4 February 2008 74 of 77 NXP Semiconductors TDA8295 Digital global standard low IF demodulator for analog TV and FM radio Abbreviations ...continued Description Incidental Carrier Phase Modulation IDentification Intermediate Frequency Neighbor Picture Carrier Neighbor Sound Carrier Picture Carrier Printed-Circuit Board Phase-Locked Loop Pulse Width Modulation Quasi Split Sound Surface Acoustic Wave Sound Carrier Surface Mounted Device Second Sound Intermediate Frequency Set-Top Box Test Access Port Video Cassette Recorder Vertical Interval Test Signal Table 74. Acronym ICPM ID IF NPC NSC PC PCB PLL PWM QSS SAW SC SMD SSIF STB TAP VCR VITS 18. Revision history Table 75. Revision history Release date 20080204 Data sheet status Product data sheet Change notice Supersedes Document ID TDA8295_1 TDA8295_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 4 February 2008 75 of 77 NXP Semiconductors TDA8295 Digital global standard low IF demodulator for analog TV and FM radio 19. Legal information 19.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 19.2 Definitions Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 19.3 Disclaimers General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected 19.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus -- logo is a trademark of NXP B.V. Silicon Tuner -- is a trademark of NXP B.V. 20. Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: salesaddresses@nxp.com TDA8295_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 4 February 2008 76 of 77 NXP Semiconductors TDA8295 Digital global standard low IF demodulator for analog TV and FM radio 21. Contents 1 2 3 4 5 6 7 7.1 7.2 8 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 9 9.1 9.1.1 9.1.2 9.2 9.3 9.3.1 9.3.2 9.3.3 9.3.4 9.3.5 9.3.6 9.3.7 9.3.8 9.3.9 9.3.10 9.3.11 9.3.12 9.3.13 9.3.14 9.3.15 9.3.16 9.3.17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Quick reference data . . . . . . . . . . . . . . . . . . . . . 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 7 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 8 Functional description . . . . . . . . . . . . . . . . . . 10 IF ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 PLL demodulator . . . . . . . . . . . . . . . . . . . . . . 10 Nyquist filter, video low-pass filter, video and group delay equalizer, video leveling . . . . 10 Upsampler and video DAC . . . . . . . . . . . . . . . 11 SSIF/mono sound processing. . . . . . . . . . . . . 11 Tuner IF AGC . . . . . . . . . . . . . . . . . . . . . . . . . 11 Digital IF AGC. . . . . . . . . . . . . . . . . . . . . . . . . 12 Clock generation. . . . . . . . . . . . . . . . . . . . . . . 12 2C-bus control . . . . . . . . . . . . . . . . . . . . . . . . . 12 I Protocol of the I2C-bus serial interface . . . . . . 12 Write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Register overview . . . . . . . . . . . . . . . . . . . . . . 15 Register description . . . . . . . . . . . . . . . . . . . . 20 Standard setting with easy programming . . . . 20 Diverse functions (includes tuner IF AGC Pin mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 ADC headroom . . . . . . . . . . . . . . . . . . . . . . . . 23 Picture carrier PLL functions . . . . . . . . . . . . . 24 Picture and sound carrier DTO . . . . . . . . . . . . 27 Filter settings . . . . . . . . . . . . . . . . . . . . . . . . . 28 Group delay equalization . . . . . . . . . . . . . . . . 30 Digital IF AGC functions . . . . . . . . . . . . . . . . . 31 Tuner IF AGC functions . . . . . . . . . . . . . . . . . 33 V-sync adjustment . . . . . . . . . . . . . . . . . . . . . 34 CVBS settings. . . . . . . . . . . . . . . . . . . . . . . . . 35 SSIF and mono sound settings. . . . . . . . . . . . 37 Status registers: ADC saturation, AFC, H/V PLL and AGC. . . . . . . . . . . . . . . . . . . . . . 39 Debug register for ADC and DAC test . . . . . . 41 Chip identification and Standby mode . . . . . . 41 Status of clock PLL and video/sound DAC load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 ADC control . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9.3.18 9.3.19 9.3.20 10 11 12 13 13.1 13.2 13.3 13.4 13.5 13.5.1 13.5.2 13.6 13.7 14 14.1 15 16 16.1 16.2 16.3 16.4 17 18 19 19.1 19.2 19.3 19.4 20 21 Video and sound DAC control . . . . . . . . . . . . Clock generation (PLL and crystal oscillator). GPIOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Limiting values . . . . . . . . . . . . . . . . . . . . . . . . Thermal characteristics . . . . . . . . . . . . . . . . . Characteristics . . . . . . . . . . . . . . . . . . . . . . . . Application information . . . . . . . . . . . . . . . . . Typical application . . . . . . . . . . . . . . . . . . . . . Detailed application diagram . . . . . . . . . . . . . DAC connection . . . . . . . . . . . . . . . . . . . . . . . ADC connection . . . . . . . . . . . . . . . . . . . . . . . Reset operation . . . . . . . . . . . . . . . . . . . . . . . Hardware reset. . . . . . . . . . . . . . . . . . . . . . . . Software reset . . . . . . . . . . . . . . . . . . . . . . . . Application hints . . . . . . . . . . . . . . . . . . . . . . . Crystal connection . . . . . . . . . . . . . . . . . . . . . Test information. . . . . . . . . . . . . . . . . . . . . . . . Boundary scan interface ("IEEE Std. 1149.1") Package outline . . . . . . . . . . . . . . . . . . . . . . . . Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction to soldering. . . . . . . . . . . . . . . . . Wave and reflow soldering . . . . . . . . . . . . . . . Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 46 49 51 51 52 63 63 64 65 65 66 66 66 66 67 68 68 71 72 72 72 72 73 74 75 76 76 76 76 76 76 77 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'. (c) NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 4 February 2008 Document identifier: TDA8295_1 |
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